Kurt Schweiger

Pulse Shape Measurements by On-Chip Sense Amplifiers of Single Event Transients Propagating Through a 90 nm Bulk CMOS Inverter Chain

Single event transient (SET) pulse shapes caused by Au ions with an energy of 946 MeV were measured at the microprobe facility at GSI in Darmstadt. Using on-chip sense amplifiers, our novel approach allows observing SET pulse shapes at any interesting circuit node with negligible distortion. We were hence able to accurately trace the propagation of SET pulses through a 90 nm CMOS inverter chain.

Supply Voltage Dependent On-Chip Single-Event Transient Pulse Shape Measurements in 90-nm Bulk CMOS Under Alpha Irradiation

Direct on-chip pulse shape measurements of single-event transients (SETs) in a single inverter in 90-nm bulk CMOS have been performed at the microbeam facility at the Physikalisch-Technische Bundesanstalt (PTB), Braunschweig, Germany. Alpha particles with an energy of 8 MeV were used as projectiles, and the supply voltage dependence of the arising SETs was investigated. A strong dependence of the resulting pulse heights, widths, and shapes on the supply voltage could be observed.

A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm CMOS

The offer of information grows rapidly in mobile markets. The DVB-H standard as a part of DVB-T is an important carrier of information to a broad spectrum of consumers. New, cheap and robust receivers have to be developed, especially for handheld devices. We propose a high-speed operational amplifier for a low-pass filter in a direct conversion receiver. In order to integrate the receiver on a System on Chip, it is designed in 65nm low-power CMOS. The operational amplifier is a four-stage feed-forward nested Miller compensated fully differential operational amplifier with an AB output stage. A gain-bandwidth product of 1GHz and a gain of 58dB is reached. A load capacitance of 5pF can be driven at a phase margin of 62deg.

Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology

A highly linear down-conversion mixer in a 65 nm digital CMOS technology is presented. The mixer was fabricated in a tripple-well process which allows to use the bulk of NMOS transistors as inputs. In contrary to other works not the gate but the bulk connector is used for the input signal. A high IIP3 of +18 dBm was achieved with a power consumption of only 0.67 mW from a 1.2 V supply voltage. The mixer has a measured ldB compression point of +7 dBm. The input signal bandwidth lies beyond 2 GHz.

Experimental Validation of a Faithful Binary Circuit Model

Fast digital timing simulations based on continuous-time, digital-value circuit models are an attractive and heavily used alternative to analog simulations. Models based on analytic delay formulas are particularly interesting here, as they also facilitate formal verification and delay bound synthesis of complex circuits. Recently, Függer et al. (arXiv:1406.2544 [cs.OH]) proposed a circuit model based on so-called involution channels. It is the first binary circuit model that realistically captures solvability of short-pulse filtration, a non-trivial glitch propagation problem related to building one-shot inertial delays. In this work, we address the question of whether involution channels also accurately model the delay of real circuits. Using both Spice simulations and physical measurements, we confirm that modeling an inverter chain by involution channels accurately describes reality. We also demonstrate that transitions in vanishing pulse trains are accurately predicted by the involution model. For our Spice simulations, we used both UMC-90 and UMC-65 technology, with varying supply voltages from nominal down to near sub-threshold range. The measurements were performed on a special-purpose UMC-90 ASIC that combines an inverter chain with low-intrusive high-speed on-chip analog amplifiers.

A mixer-filter combination of a direct conversion receiver for DVB-H applications in 65nm CMOS

A mixer and operational amplifier filter combination in 65 nm CMOS technology for DVB-H is presented. Special focus is laid on the design of the operational amplifier, which is a nested-Miller compensated, 3-stage feed-forward operational amplifier. Characteristic of the operational amplifier is the supply voltage of 2.5 V to enlarge the output signal swing of the operational amplifier. Cascodes are used avoiding the electrical destruction. The operational amplifier has a gain of 89 dB, a gain-bandwidth of 1.1 GHz, and phase margin of 53.3 deg at a load of 1 pF on each of the two differential outputs. The current consumption is 5.85 mA. This operational amplifier is used in a first-order low-pass filter after a passive mixer. This mixer-filter combination is characterized as well. A conversion gain of 24 dB and a bandwidth of 4 MHz are realized. Furthermore a noise figure of 16.1 dB and an IIP3 of +10dBm are achieved.

Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOS

An innovative design with simulation results of a low-voltage bulk driven mixer for direct conversion receiver is presented. The circuit is designed in a 65nm digital CMOS process without analog extensions. It offers a conversion gain of 22dB at a clock frequency of 1.5GHz for GALILEO/GPS applications. The design is capable of operating at up to 7GHz with only 3dB gain decrease. The simulated noise figure is 27dB with a power consumption of 730µW. Simulations at a supply voltage of 0.9V instead of 1.2V show a gain decrease of only 3dB while the noise figure increases by 2dB.

Building reliable systems-on-chip in nanoscale technologies

Modern application-specific integrated circuits (ASICs) contain complete systems on a single die, composed of many processing elements that communicate over a dedicated router-based on-chip network. As systems-on-chip comprise billions of transistors with feature sizes in the range of 10 nm, reliable operation cannot be established without carefully engineered support at all levels, from technology to the circuit- and the system-layer. This article surveys contributions of research groups at TU Wien to this field. At lower levels of abstraction, they range from the generation of fault models for simulation that closely match reality and are at the same time efficient to use, to circuit-level radiation-tolerance techniques. At the level of on-chip networks, novel fault-tolerant routing algorithms are being developed together with architectural techniques to isolate faulty parts while keeping the healthy parts connected and active.The article will briefly portray the associated research activities and summarize their most relevant results.ZusammenfassungModerne anwendungsspezifische integrierte Schaltungen (ASICs) beinhalten auf einem einzigen Chip ganze Systeme, bestehend aus einer Vielzahl an Funktionsblöcken, die über eigene Router-basierte “On-chip”-Netzwerke kommunizieren. Der zuverlässige Betrieb eines solchen Milliarden an Transistoren mit Feature-Size in Bereich von 10 nm umfassenden Systems kann nur durch sorgfältig ausgelegte Maßnahmen auf allen Ebenen, von der Technologie über das Schaltungsdesign bis hin zur Systemebene, gewährleistet werden. Der vorliegende Artikel gibt einen Überblick über die diesbezüglichen Beiträge der Forschergruppen an der TU Wien. Auf den unteren Abstraktionsebenen reichen diese von der Erstellung möglichst wirklichkeitsgetreuer Fehlermodelle für die Simulation, die dennoch handhabbar bleiben, bis hin zu schaltungstechnischen Maßnahmen zur Erhöhung der Strahlungsfestigkeit. Auf der Ebene der On-chip-Netzwerke werden neuartige fehlertolerante Routing-Algorithmen in Kombination mit Architekturmaßnahmen entwickelt, die fehlerhafte Bereiche isolieren, während funktionierende Teile verbunden und aktiv bleiben.Der Artikel umreißt die entsprechenden Forschungsaktivitäten und skizziert ihre wichtigsten Ergebnisse.

Highly linear down-conversion mixer in 65nm CMOS for a high supply voltage of 2.5V

A direct down conversion Gilbert-type mixer in combination with an active low-pass filter for 4MHz is presented. The Gilbert-type mixer is enhanced with a source degeneration to improve the linearity performance. The active filter is a linearity enhanced differential amplifier with feedback network. For the high supply voltage of 2.5V additional over-voltage protection with cascodes is added to the circuit parts. The entire receiver part consumes 6.88mA from a 2.5V supply. A high gain of 26.6dB is achieved by the active mixer in combination with the active filter. The noise figure of the entire circuit is only 11.8dB. The input referred intercept point of 3rd-order is +18.6dBm.

A 65nm CMOS down-sampling micromixer with enhanced DC current capability

This paper presents a low power CMOS down sampling micromixer in 65nm with an improved input stage. It is able to handle a superimposed DC current on the input port without degrading circuit performance. The mixer was fabricated in a triple-well process. A conversion gain of 17dB is achieved while only consuming 780muW from a 1.2V voltage supply up to a 3dB clock frequency of 600MHz. The gain decreases for 3dB at a superimposed DC current of 210muA. The 1dB compression point and IIP3 are measured to be -22.7dBm and -16dBm, respectively.