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Dive into the research topics where Varadan Savulimedu Veeravalli is active.

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Featured researches published by Varadan Savulimedu Veeravalli.


digital systems design | 2012

Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip

Varadan Savulimedu Veeravalli; Thomas Polzer; Andreas Steininger; Ulrich Schmid

This paper presents the architecture and a detailed design analysis of a digital measurement chip which facilitates long-term irradiation experiments of basic asynchronous circuits. It combines radiation targets like Muller C-elements and elastic pipelines as well as standard combinational gates and flip-fops with an elaborate on-chip measurement infrastructure. Major architectural challenges result from the fact that the latter must operate reliably under the same radiation conditions the target circuits are exposed to, without wasting precious die area for a rad-hard design. A measurement architecture based on multiple non-rad-hard counters is used, which we show to be resilient against double faults, as well as many triple and even higher-multiplicity faults. The analysis is done by means of comprehensive fault injection experiments, which are based on detailed Spice models of the circuits in conjunction with a standard double-exponential current injection model for single-event transients. We also provide probabilistic calculations of the sustainable particle flow rates, based on the results of a detailed area analysis in conjunction with experimentally determined cross section data for the ASIC implementation technology used. The results confirm that the overall architecture indeed supports significant target hit rates, without exceeding the resilience bound of the measurement infrastructure.


international conference on computer design | 2014

Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example

Andreas Steininger; Varadan Savulimedu Veeravalli; Dan Alexandrescu; Enrico Costenaro; Lorena Anghel

Asynchronous circuits exhibit considerable advantages over their synchronous counterparts, like lower dynamic power and inherent variation tolerance, which makes them increasingly interesting. Their fault-tolerance behavior, however, is not yet fully explored. In particular, temporal masking, as seen with synchronous circuits, seems to be completely non-existent in asynchronous logic. Instead, there seem to be other masking mechanisms in the control structure that establish an extra barrier for transient fault propagation. In this paper we will explore these masking mechanisms in a qualitative as well as quantitative manner. To this end we first analyze the behavior of a Muller C-element, one fundamental building block in asynchronous designs. In a next step we evaluate the behavior of a chain of these elements, forming a so-called Muller pipeline, the basic control structure of many asynchronous designs, under transient faults. To validate our theoretical findings we inject radiation induced single event transients (SETs) in an extensive simulation campaign. The results show that the SET susceptibility of the Muller pipeline is indeed state dependent. This knowledge can be leveraged to improve, e.g., the radiation hardness of asynchronous circuits by preferring the more robust states in their design wherever possible.


international symposium on quality electronic design | 2014

Architecture for monitoring SET propagation in 16-bit Sklansky adder

Varadan Savulimedu Veeravalli; Andreas Steininger

We propose a measurement architecture that allows to trace generation and propagation of single-event transients in a combinational target circuit that will be subjected to radiation in an experimental study. We choose the Sklansky adder as a target circuit, since it exhibits both properties we are interested in, namely different amounts of fanout and a carry propagation chain. The problem of devising a suitable on-chip measurement infrastructure lies in the partly contradictory requirements, like constrained area, radiation tolerance and good resolution of the location and propagation path of particle hits. Our proposed architecture is based on linear feedback shift registers that can be used as lean and robust counter implementations. These counters are attached at selected locations within the target adder circuit, and we show by means of a simulation study as well as a fault dictionary that this architecture indeed comes up to our expectations.


international symposium on quality electronic design | 2014

Measuring SET pulsewidths in logic gates using digital infrastructure

Varadan Savulimedu Veeravalli; Andreas Steininger; Ulrich Schmid

We present a purely digital infrastructure for measuring SET pulsewidths in logic gates. Such a facility is crucial for experimentally studying radiation sensitivity and SET propagation of a circuit. Our digital-only implementation facilitates measurement within a standard-cell CMOS chip, without the need of any analog or customized circuitry on-chip. Besides high resolution and area efficiency, a fundamental requirement guiding the development of our solution was radiation tolerance, as it shall be employed on a test chip that is fully exposed to radiation in an experimental study. We validate our architecture, for various primary radiation target circuits, by analog simulation, injecting SETs of varying strength using the standard double-exponential current model.


ieee aerospace conference | 2013

Performance of radiation hardening techniques under voltage and temperature variations

Varadan Savulimedu Veeravalli; Andreas Steininger

The effectiveness of the techniques to mitigate radiation particle hits in digital CMOS circuits has been mainly studied under a given set of environmental conditions. This paper will explicitly analyze, how the performance of two selected radiation hardening techniques, namely transistor sizing and stack separation, varies with temperature and supply voltage. Our target is an inverter circuit in UMC90 bulk CMOS technology, instances of which have been hardened against charges of 300fC and 450fC using either of the two techniques under investigation. In a Spice simulation we apply particle hits to these circuits through double-exponential current pulses of the respective charge. We study the effect of these pulses in a temperature range from −55 C to +175 C and a supply voltage of 0.65 to 1.2V (nominal 1V) at the output of a (unhardened) buffer that has been connected as a load. For the hardening by sizing we observe proper operation in the range from 1.2V to 900mV, while for lower supply we observe full swing pulses of increasing magnitude when the respective maximum charge is applied. The influence of temperature turns out to be minor. For the stack separation approach the observation is similar, however, the circuit starts glitching only at 750mV. Our study allows the following conclusions: (i) The effectiveness of the hardening approaches strongly depends on the supply voltage, and moderately on temperature. (ii) As expected, low voltage and high temperature represent the worst case for rad-hard sizing. Stack separation, on the other hand, unexpectedly shows a stronger and more complicated temperature dependence. (ii) For voltages below approx. 90% of nominal the hardening by sizing fails, when designed for nominal voltage and room temperature. The approach can be enhanced to survive this worst case by increasing the sizing factor further by more than 3 times. (iv) The stack separation only fails for voltages below approx. 75% of nominal, but there is no simple remedy to make it reliable for a larger range. This must be considered when judging the appropriateness of this method for a given purpose. Also it turned out that once it fails, the resulting SET pulse has considerable length.


design and diagnostics of electronic circuits and systems | 2012

Radiation-tolerant combinational gates - an implementation based comparison

Varadan Savulimedu Veeravalli; Andreas Steininger

As newer CMOS technologies are known to be more susceptible to particle hits, radiation tolerance is receiving increased attention. Several techniques for attaining this property are available in the literature already. However, virtually all of the publications refer to an inverter circuit, and the related robustness assessments (if any) are hard to compare, since important characteristics, such as technology or fault model, differ. In this paper we fill this gap by applying the available concepts to combinational gates, in particular an XOR gate, using the same concrete technology and sizing as well as the same fault model. By means of extensive analog simulations we verify and finally tune their robustness to the same level. On this foundation we can then make a comparison of the respective overheads and problems, such that it becomes relatively easy to distinguish efficient solutions from problematic ones.


digital systems design | 2016

Design and Physical Implementation of a Target ASIC for SET Experiments

Varadan Savulimedu Veeravalli; Andreas Steininger

We present design aims and implementation results of a digital ASIC that is dedicated as a target for radiation experiments. Accordingly, it carries different target circuit blocks whose purpose is to study susceptibility to radiation as well as propagation of radiation effects. On-chip measurement infrastructure is mainly comprised of counters that record single event transients in various nodes of the target blocks. As it competes with the target blocks for chip area, it must be kept as small as possible, in spite of the need of being tolerant to particle hits in itself, which cannot be avoided in some types of radiation experiments. We sketch our respective solutions and present the resulting area distribution of the final ASIC layout for an industrial 65nm bulk CMOS process. We also show how we optimized the layout for the purpose of our experiments and present all relevant implementation details.


ieee international symposium on asynchronous circuits and systems | 2013

Modular Redundancy in a GALS System Using Asynchronous Recovery Links

Jakob Lechner; Varadan Savulimedu Veeravalli

In this paper we describe a new design approach for fault-tolerant globally asynchronous locally synchronous (GALS) systems using triple modular redundancy. The paper proposes a recovery and voting mechanism that relies on asynchronous, delay-insensitive links for state exchange. Thereby the replicated module copies remain fully timing-independent and only need to be locally synchronized. This allows for extremely flexible module partitioning and placement: Triplicated modules could be arranged on a single die, or be mapped to three separate chips to minimize the risk of two copies failing at the same time. In the first part of the paper we discuss the general concept of the recovery mechanism and the requirements for the design of the GALS modules to ensure replica determinism. The second part of the paper then presents the implementation of a lightweight recovery controller, which consists of both synchronous and asynchronous components. To access the internal state of a module we re-use the scan chains, which are typically included in every synchronous circuit for testing purposes. The robustness of our solution is verified by exhaustive fault-injection experiments.


digital systems design | 2017

Setup for an Experimental Study of Radiation Effects in 65nm CMOS

Bernhard Fritz; Andreas Steininger; Vaclav Simek; Varadan Savulimedu Veeravalli

Physical radiation experiments are a vital means for calibrating simulation models targeted to studying the impact of ionizing particles on VLSI circuits. However, their conduction requires special care and a very specific setup. In this paper we give an overview of such an experimental setup, and highlight some specific details. Beyond showing the context overarching the objectives of the experiments, the envisioned radiation sources, as well as design and architecture of a specific target ASIC, we will put specific emphasis on the communication infrastructure, namely an FPGA that controls the data exchange between some preprocessing infrastructure located on the target ASIC on one side and the host PC running the data analysis on the other. Finally, the physical arrangement comprising carrier PCB for the target ASIC, and cabling, which need to adhere specific requirements, will receive some attention as well.


Microprocessors and Microsystems | 2017

A versatile architecture for long-term monitoring of single-event transient durations

Varadan Savulimedu Veeravalli; Andreas Steininger; Ulrich Schmid

We present design and analysis of an on-chip measurement infrastructure, which facilitates long-term monitoring of single-event transient durations in digital VLSI circuits exposed to uncontrollable radiation. Unlike the known oscilloscope-based methods, our approach is all-digital: SET durations are measured by the SET-gated counting of pulses generated by a high-frequency ring oscillator, and stored in an up/down-counter array organized in a ring. We carefully elaborate a comprehensive concept for making our infrastructure SEU tolerant, with the main challenge being to attain a sufficiently high probability of recording useful hits in the target before exhausting the SEU tolerance of the infrastructure. Our key contribution here concerns the protection of the counter array: Rather than resorting to radiation hardening or explicit triple modular redundancy (TMR), we save area by using a novel redundant duplex counter architecture: For a small number of recorded SETs, our architecture implicitly implements TMR, albeit in a way that degrades gracefully for larger numbers of recorded SETs. Besides standard functional and timing verification, we use Spice-based SET injection for verifying the effectiveness of our SEU-tolerant architecture, and some cross section-based probabilistic analysis for confirming that our measurement infrastructure based on it indeed achieves its purpose.

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Dive into the Varadan Savulimedu Veeravalli's collaboration.

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Andreas Steininger

Vienna University of Technology

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Ulrich Schmid

Vienna University of Technology

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Horst Zimmermann

Vienna University of Technology

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Kurt Schweiger

Vienna University of Technology

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Michael Hofbauer

Vienna University of Technology

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Thomas Polzer

Vienna University of Technology

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Axel Jantsch

Vienna University of Technology

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Horst Dietrich

Vienna University of Technology

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Jakob Lechner

Vienna University of Technology

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