Kush Gulati

A low-power reconfigurable analog-to-digital converter

A reconfigurable analog-to-digital converter digitizes signals over a 1 Hz-10 MHz bandwidth and 6 to 16 b resolution with adaptive power consumption. The converter achieves this by reconfiguring between pipeline and /spl Delta//spl Sigma/ architectures and adjusting circuit parameters and bias currents.

A high-swing CMOS telescopic operational amplifier

A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. The resulting degradation in differential gain, common-mode rejection ratio (CMRR), and other amplifier characteristics are compensated by applying regulated-cascode differential gain enhancement and a replica-tail feedback technique. A prototype of the op-amp has been built in a 0.81-/spl mu/m CMOS process. Operating from a power supply of 3.3 V, it achieves a differential swing of /spl plusmn/2.15 V, a differential gain of 90 dB, unity-gain frequency of 90 MHz, and >50-dB CMRR. It is shown, analytically and through simulations, that the operational amplifier maintains its high CMRR even at high frequencies.

A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs

A CMOS analog baseband transceiver with a 13-bit, 180 MSPS pipelined ADC and dual 12-bit, 180 MSPS current-steering DACs is presented. The ADC is implemented without a dedicated track-and-hold stage, utilizes a front-end 2.5-bit stage with matched MDAC/comparator tracking circuits, and demonstrates an ENOB of 10.6 bits at 15 MHz and 9.7 bits at 100 MHz, employing a low-jitter delay-lock loop for its phasing. The dual I/Q DACs show over 62 dB SFDR over the Nyquist band by utilizing a dynamic linearity enhancing architecture

A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration

A 12 bit 200 MS/s analog-to-digital converter (ADC) applies techniques of zero-crossing-based circuits as a replacement for high-gain high-speed op-amps. High accuracy in the residue amplifier is achieved by using a coarse phase in ZCBC followed by a level-shifting capacitor for fine phase. Sub-ADC flash comparators are strobed immediately after the coarse phase to achieve a high sampling rate. The systematic offset voltage between the coarse and fine phase manifests itself as systematic offset in the sub-ADC comparators. This offset is caused by the coarse phase undershoot and the fine phase overshoot. In this work, the offset is cancelled with background calibration by residue range correction circuits in the following stages sub-ADC. In addition, the sub-ADCs random comparator offset is calibrated with a discrete-time charge-pump based background calibration technique. The reference buffer, bias circuitry, and digital error correction circuits are all integrated on a single chip. The ADC occupies an area of 0.282 mm 2 in 55 nm CMOS technology and dissipates 30.7 mW. It achieves 64.6 dB SNDR and 82.9 dBc SFDR at 200 MS/s for a FOM of 111 fJ/conversion-step. The SNDR degrades gracefully above the designed sampling frequency to 62.9 dB at 250 MS/s, and remains above 50 dB at 300 MS/s.

A highly-integrated CMOS analog baseband transceiver with 180MSPS 13b pipelined CMOS ADC and dual 12b DACs

The 180MSPS, 13b CMOS pipelined ADC of a transceiver is implemented without a dedicated track-and-hold stage and utilizes a front-end 2.5b stage with matched MDAC/comparator tracking circuits. The ADC demonstrates ENOB of 10.6b at 15MHz and 9.7b at 100MHz. It employs a low-jitter delay-lock loop for its phasing. The dual I/Q 12b 180MSPS DACs show over 62dB SFDR over the Nyquist band by utilizing a dynamic linearity enhancing architecture.

11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR

Pipeline ADCs have traditionally served as a general-purpose architecture for high-speed and high-resolution applications such as medical and wireless receivers. Recently, achieving the highest levels of linearity with ultra-low power consumption has proven to be extremely challenging using modern CMOS technology with limited headroom. While zero-crossing-based circuits (ZCBC) have proven to be a power-efficient alternative to opamps in pipeline ADCs, performance using zero-crossing techniques have to-date only been demonstrated with ENOB ≤11. This paper presents a 15b 48MS/s zero-crossing-based pipeline ADC that achieves low power consumption of 99fJ/step and high linearity performance of 73.1dB SNDR and >80dB SFDR at Nyquist, demonstrating state-of-the-art FoM for thermal-noise-limited designs of 165.1dB.

A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS

A 12-bit 200MS/s zero-crossing based pipeline ADC is presented. A coarse phase followed by a level-shifted fine phase is employed for higher accuracy. To enable high frequency operation, sub-ADC flash comparators are strobed immediately after the coarse phase. The ADC occupies 0.276mm2 in 55nm CMOS and dissipates 28.5mW. 62.5dB SNDR and 78.6dBc SFDR with a 99.6MHz input signal at 200MS/s are achieved for a FOM of 131fJ/step. The reference buffer, bias circuitry, and digital error correction circuits are all implemented on chip.

A /spl plusmn/2.45 V-swing CMOS telescopic operational amplifier

This telescopic opamp offers higher output swing than a conventional telescopic amplifier while maintaining high CMRR and supply rejection (PSRR), and ensuring constant performance parameters. Transistors are deliberately driven deep into the linear region. The output swing is improved by 0.7V from a telescopic amplifier and becomes comparable to a folded cascode amplifier. The reduction of gain and CMRR due to the low output resistance in the linear region is compensated by gain enhancement and replica tail feedback, respectively.

F6: Circuit, systems and data processing for next-generation wearable and implantable medical devices

There are exciting new developments in health care wearables, fitness trackers and therapeutic implantable devices. This advancement is fueled, in part, by the miniaturization of sensors and associated electronics. One of the greatest opportunities in wearables and implanted devices is the wealth of data that can be extracted from these devices and the high-quality information that can emerge by combining data from multiple sources for effective utilization by physicians. Longitudinal data, generated by continuous monitoring of physiological and vital parameters, can increase therapy efficacy and lead to the invention of new biomarkers. However, continuous and unobtrusive monitoring requires extreme miniaturization and minimal dependence on energy constraints. This creates challenges on integrated circuits and requires new techniques directed towards lowering energy consumption and reducing area and volume. This forum will provide an overview of the challenges of the various systems, circuits and heterogeneous technologies that are essential for building next generation on- and in-body medical devices.