Soon-Kyun Shin

A slew-rate controlled output driver using PLL as compensation circuit

A slew rate controlled output driver adopting delay compensation method is implemented using 0.18 µm CMOS process for storage device interface. Phase-Locked Loop is used to generate compensation current and constant delay time. Compensation current reduces the slew rate variation over process, voltage and temperature variation in output driver. To generate constant delay time, the replica of VCO in PLL is used in output drivers slew rate control block. That reduces the slew rate variation over load capacitance variation. That has less 25% variation at slew rate than that of conventional output driver. The proposed output driver can satisfy UDMA100 interface which specify load capacitance as 15 ∼ 40pF and slew rate as 0.4 ∼ 1.0[V/ns].

A fully-differential zero-crossing-based 1.2V 10b 26MS/s pipelined ADC in 65nm CMOS

A fully-differential zero-crossing-based 10b 26 MS/s pipelined ADC in a 65 nm CMOS process is presented. Switched-capacitor overshoot correction is compatible with the differential topology and allows faster operation. A CMFB is engaged in the coarse phase for constant common-mode. The 0.33 mm2 ADC achieves 54.3 dB SNDR with a FOM of 161 fJ/step.

A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration

A 12 bit 200 MS/s analog-to-digital converter (ADC) applies techniques of zero-crossing-based circuits as a replacement for high-gain high-speed op-amps. High accuracy in the residue amplifier is achieved by using a coarse phase in ZCBC followed by a level-shifting capacitor for fine phase. Sub-ADC flash comparators are strobed immediately after the coarse phase to achieve a high sampling rate. The systematic offset voltage between the coarse and fine phase manifests itself as systematic offset in the sub-ADC comparators. This offset is caused by the coarse phase undershoot and the fine phase overshoot. In this work, the offset is cancelled with background calibration by residue range correction circuits in the following stages sub-ADC. In addition, the sub-ADCs random comparator offset is calibrated with a discrete-time charge-pump based background calibration technique. The reference buffer, bias circuitry, and digital error correction circuits are all integrated on a single chip. The ADC occupies an area of 0.282 mm 2 in 55 nm CMOS technology and dissipates 30.7 mW. It achieves 64.6 dB SNDR and 82.9 dBc SFDR at 200 MS/s for a FOM of 111 fJ/conversion-step. The SNDR degrades gracefully above the designed sampling frequency to 62.9 dB at 250 MS/s, and remains above 50 dB at 300 MS/s.

A Fully Integrated, Regulatorless CMOS Power Amplifier for Long-Range Wireless Sensor Communication

This paper presents a CMOS power amplifier (PA) system designed with the explicit goal of customizing a high-output power transmitter for sensor applications, where the supply voltage from an energy storage element is often time varying. The PA is intended for use in a long-range sensor transceiver and can operate directly off a super-capacitor source. A constant output-power, regulatorless, series power-combined PA with a fully integrated tunable matching network is implemented in an attempt to eliminate all energy losses associated with a high-current voltage regulator. The PA monitors the output voltage at the off-chip antenna and digitally modulates the PA load impedance to maintain a constant target output power as the super-capacitor discharges. The PA system, integrated in a 90-nm CMOS process, has a peak output power of 24 dBm with an efficiency of 12% at 1.8 GHz, making it suitable for sensor data communication over distances of several hundred meters. As the PA supply varies from 2.5 to 1.5 V, the power control loop maintains a constant output power with an accuracy of

A high current driving charge pump with current regulation method

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11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR

0.8 dB.

A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS

This paper proposes a charge pump having a high driving capability for driving more than a load of 8 mA with a 5 V regulated output voltage. The output of the charge pump generates 5 V without any damages to the oxide using protection circuits, even though it uses 3 V MOS transistors. The prototype chip designed using 0.13 /spl mu/m CMOS process provides the range of a 0/spl sim/25 mA load current and generates a well regulated 5 V output voltage with a flying capacitor of 500 nF and clock frequency of 500 KHz. The chip area is 0.21 mm/sup 2/. The power efficiency is as much as 86% at 3.0 V supply.

A slew rate-controlled output driver having a constant transition time over the variations of process, voltage and temperature

Pipeline ADCs have traditionally served as a general-purpose architecture for high-speed and high-resolution applications such as medical and wireless receivers. Recently, achieving the highest levels of linearity with ultra-low power consumption has proven to be extremely challenging using modern CMOS technology with limited headroom. While zero-crossing-based circuits (ZCBC) have proven to be a power-efficient alternative to opamps in pipeline ADCs, performance using zero-crossing techniques have to-date only been demonstrated with ENOB ≤11. This paper presents a 15b 48MS/s zero-crossing-based pipeline ADC that achieves low power consumption of 99fJ/step and high linearity performance of 73.1dB SNDR and >80dB SFDR at Nyquist, demonstrating state-of-the-art FoM for thermal-noise-limited designs of 165.1dB.

A long-range, fully-integrated, regulator-less CMOS power amplifier for wireless sensor communications

A 12-bit 200MS/s zero-crossing based pipeline ADC is presented. A coarse phase followed by a level-shifted fine phase is employed for higher accuracy. To enable high frequency operation, sub-ADC flash comparators are strobed immediately after the coarse phase. The ADC occupies 0.276mm2 in 55nm CMOS and dissipates 28.5mW. 62.5dB SNDR and 78.6dBc SFDR with a 99.6MHz input signal at 200MS/s are achieved for a FOM of 131fJ/step. The reference buffer, bias circuitry, and digital error correction circuits are all implemented on chip.

Output buffer for reducing slew rate variation

A slew rate-controlled output driver using capacitive feedback is described in this paper. To make a constant transition time in the output driver, a constant current source is used with capacitive feedback between output and the gate of output driver. The capacitor feedback path gives a current path which connects the gate of the output driver with the output during the output drivers transition period to sustain a constant slew rate. The proposed output driver was designed using a 0.13 /spl mu/m CMOS process. According to our evaluation, the transition time variation of the proposed output driver due to PVT variations is improved by 92% compared to the conventional output driver, and the variation due to the output load variation of 10/spl sim/100 pF in typical process, voltage and temperature condition is also improved by as much as 467 %.