Hong-Seon Yang

Highly Reliable and Scalable Tungsten Polymetal Gate Process for Memory Devices Using Low-Temperature Plasma Selective Gate Reoxidation

We applied a very low-temperature plasma-type selective gate reoxidation process to W/poly-Si gate for suppression of abnormal oxidation of a low contact resistive WSix/WN diffusion barrier. The device with the plasma selective gate reoxidation showed superior gate oxide reliability and improved stress immunity of transistor compared to the thermally selective gate reoxidized devices

Roles of Ti, TiN, and WN as an Interdiffusion Barrier for Tungsten Dual Polygate Stack in Memory Devices

Tungsten dual polygate (W-DPG) stacks with diffusion barriers formed by the Ti(N) process were investigated in terms of gate contact resistance (Rc) and the polydepletion effect. The Ti layer in the Ti/WN diffusion barrier is found to be converted into a TiSix/TiN bilayer during the postdeposition annealing process. The TiSix reaction between Ti and p+ polycrystalline silicon (poly-Si) effectively prevents the formation of a parasitic dielectric layer, which could lead to low-gate Rc. The TiN reaction between Ti and WN minimizes the occurrence of the TiSix reaction, which effectively reduces p+ polydepletion caused by the out-diffusion of boron during the postdeposition annealing process. Therefore, poly-Si/Ti/WN/W could be a promising tungsten dual polygate stack, which satisfies high-speed requirements in dynamic random-access memory (DRAM) devices.

Gate Oxide Reliability Characterization of Tungsten Polymetal Gate with Low-Contact-Resistive WSix/WN Diffusion Barrier in Memory Devices

Gate oxide reliability characteristics using different diffusion barrier metals for a tungsten polycrystalline silicon (poly-Si) gate stack were investigated in detail. The insertion of a thin WSix layer in a tungsten poly gate stack could effectively relieve the mechanical stress of a gate hardmask nitride film during a post thermal process, which contributes to better gate oxide reliability and the stress-immunity of the transistor. This insertion could also prevent the formation of a Si–N inter-dielectric layer, which could lower the contact resistance between poly and tungsten effectively. A W/WN/WSix/poly gate stack could be a promising candidate for a future W poly gate that shows reliable high-speed characteristics in dynamic random access memory applications.

Impact of Thin WSIX Insertion in Tungsten Polymetal Gate on Gate Oxide Reliability and Gate Contact Resistance

By inserting thin WSix layer in tungsten poly gate stack we can effectively relieve the mechanical stress of gate hard mask nitride film, which contributes to the better gate oxide reliability and stress-immunity of transistor. This insertion also could prevent the formation of Si-N dielectric layer atop poly-Si, which could lower the contact resistance between poly and tungsten effectively

Effect of selective oxidation conditions on defect generation in gate oxide

With the shrinkage of memory devices below sub-100 nm technology, the gate electrode with low resistivity is more required to improve device speed. Tungsten/polysilicon (W/poly-Si) has been widely studied due to its low resistivity. One of the problems in the W/poly-Si gate is the oxidation of W during conventional gate reoxidation in O2 ambient after gate patterning. A selective oxidation (SO) process in H2-rich H2O ambient is considered to be the solution, where Si is selectively oxidized without the oxidation of W. 1) The incorporation of hydrogen into the device, however, has a strong effect on the electrical characteristics of the device. Annealing in hydrogen ambient is used for the passivation of silicon dangling bonds in Sibased devices. 2,3) The hydrogen introduced for the passivation of these defects is known to create defects in gate oxide during a device operation. The hydrogen released into the oxide by radiation or electrical stress generates interface states and subsequently degrades the electrical characteristics of the oxide such as enhanced hot carrier degradation and negative bias temperature instability. 4,5) High-temperature annealing in N2/H2 forming gas is also reported to generate mobile hydrogenous positive ions in the oxide which can be electrically driven across the oxide. 6–8) It is therefore expected that the gate oxide reliability in the W/ poly-Si/SiO2 is also degraded by the SO process. The effect of the SO process in H2-containing ambient has, however, not reported in detail. In this paper, we report the effect of the SO process on the degradation of gate oxide in terms of stress-induced leakage current (SILC), oxide trap density, and interface state density (Dit). 2. Experimental

Effect of gate hard mask and sidewall spacer structures on the gate oxide reliability of W∕WNx∕poly‐Si gate MOSFET for high density DRAM applications

We have studied the effects of the gate hard mask and the gate spacer nitride film on the reliability of W∕WNx∕poly‐Si gated devices. When the gate hard mask nitride film is used, severe degradation of the stress-induced leakage current (SILC) and the interface trap density (Dit) characteristics are observed in the large metal-oxide-semiconductor (MOS) capacitors. On the other hand, as the devices become smaller, the effects of the hard mask nitride film are relieved. The gate spacer stack plays a more critical role in the reliability of smaller devices. The oxide∕nitride (ON) spacered devices exhibit better reliability in terms of SILC, Dit, threshold voltage (Vth) shift, and transconductance (Gm) compared to those of the nitride∕oxide∕nitride (NON) spacered ones. These behaviors are explained by the mechanical stress of the nitride films.

Physical and electrical characteristics of physical vapor-deposited tungsten for bit line process

We attempted to explain the phenomenon that the electric resistivity of tungsten film increases as the thickness decreases and that physical vapor-deposited (PVD) tungsten shows a much lower resistivity than chemical vapor-deposited (CVD) tungsten. The crystallinity and electric conductivity of an under-layer does not affect the electric resistivity of tungsten film. The low resistivity of PVD tungsten originates from a large grain size. PVD tungsten with large grains is free from grain boundary scattering, while CVD tungsten with small grains exhibits grain boundary scattering. As film thickness decreases down to the mean free path of tungsten, the surface scattering effect surpasses the grain boundary scattering effect. Consequently, the resistivity of PVD and CVD tungsten becomes equal because surface scattering increases the resistivity of both large- and small-grained films. The same rule is adaptable for the resistance change of a narrow line structure. CVD tungsten shows a high resistance because of grain boundary scattering originating from a small grain size. However, if the line-width is reduced to the mean free path, grain boundary scattering disappears, making surface scattering only the factor that increases electric resistivity. Thus, CVD tungsten shows the same resistance as PVD tungsten in a very narrow line structure.

Silicon-Based Dual-Gate Single-Electron Transistors for Logic Applications

We have fabricated silicon-based dual-gate single-electron transistors (DG-SETs) with electrically induced tunneling barriers. By utilizing e-beam lithography patterning and additional oxidation process, the device is scaled down beyond the previously demonstrated dual-gate structures. As a result, Coulomb oscillation is maintained in the large control gate bias region and its oscillation period is increased to 2.3 V. Based on the measurement, SET SPICE model is optimized and useful complementary metal–oxide–semiconductor (CMOS)/SET circuits which reduce the current oscillation period or improve peak-to-valley current ratio (PVCR) are investigated by using the model.

Influence of Hydrogen Incorporation on the Reliability of Gate Oxide Formed by Using Low-Temperature Plasma Selective Oxidation Applicable to Sub-50-nm W-Polymetal Gate Devices

This letter reveals the physical and electrical properties of silicon dioxide (Si02) formed by the plasma selective oxidation (plasma selox) using 02 and H2 gas mixture, which is applicable to sub-50-nm tungsten-polymetal gate memory devices without capping nitride film. Metal-oxide-semiconductor capacitors with gate oxide formed by the plasma selox at the process temperature in the range of 400degC-700degC showed much better time-dependent dielectric-breakdown characteristics than those formed by the conventional thermal selox at 850degC. On the other hand, in the case of very low temperature (25degC) plasma selox, the gate oxide degradation such as initial breakdown was found. It turned out to be due to the excessive hydrogen and water incorporation into the SiO2 layer through thermal desorption spectroscopy measurements.

Reliability of Recess-channel Gate Cell Transistor under Gate-Induced Drain Leakage Stress and Positive Bias Fowler-Nordheim Gate Stress

The reliability of recess-channel gate (RG) cell transistor under positive bias Fowler-Nordheim (F-N) gate stress and gate-induced drain leakage (GIDL) stress was investigated. RG cell transistor was found to be more degraded by the F-N gate stress than the GIDL stress due to the gate oxide thickness profile of the RG structure. The oxide thickness along the sidewall plane is a critical factor determining the reliability characteristics of RG cell transistor