Se-Aug Jang

Robust ternary metal gate electrodes for dual gate CMOS devices

This report describes thermally stable dual metal gate electrodes for surface channel Si CMOS devices. We found that the ternary metal nitrides, i.e., Ti/sub 1-x/Al/sub x/N/sub y/ (TiAlN) and TaSi/sub x/N/sub y/ (TaSiN) films, are stable up to 1000/spl deg/C. Especially, the stoichiometric TiAlN (y/spl sim/1) exhibited highly robust p-type gate electrode (p-TiAlN) properties, demonstrating a work function (/spl Phi//sub m/) of /spl sim/5.1 eV and excellent gate oxide integrity against the thermal budget of conventional Si CMOS processing. The N-deficient TiAlN (y < 1) showed /spl Phi//sub m/ for n-type electrode (n-TiAlN) with limited thermal stability. The dual gate electrodes, p-TiAlN and TaSiN, exhibited negligible EOT (equivalent oxide thickness) variation on the high-k gate dielectrics (ZrO/sub 2/, HfO/sub 2/) up to 950/spl deg/C.

Work function and thermal stability of Ti1−xAlxNy for dual metal gate electrodes

Work function and thermal stability of reactive sputtered Ti1−xAlxNy films were investigated for a metal gate electrode using a metal–oxide–semiconductor (MOS) structure. It is found that the work function (ΦM) values of Ti1−xAlxNy are ranged from 4.36 to 5.13 eV with a nitrogen partial flow rate (fN2). The ΦM values of Ti1−xAlxNy films, 4.36 eV for nMOS (n-Ti1−xAlxNy) and 5.10–5.13 eV for pMOS (p-Ti1−xAlxNy), may be applicable to dual metal gate electrodes. Excellent thermal stability up to 1000u200a°C was obtained on SiO2 as observed by the negligible change of capacitance equivalent thickness and Al 2p core level spectra for p-Ti1−xAlxNy (y∼1.0,fN2=50%), whereas a limited stability was attained in case of n-Ti1−xAlxNy (fN2⩽40%). The p-Ti1−xAlxNy can be a good candidate for pMOS device feasibility because of good thermal stability, while the n-Ti1−xAlxNy may be applicable for nMOS gate electrode in low thermal devices using damascene gate process.

Highly Reliable and Scalable Tungsten Polymetal Gate Process for Memory Devices Using Low-Temperature Plasma Selective Gate Reoxidation

We applied a very low-temperature plasma-type selective gate reoxidation process to W/poly-Si gate for suppression of abnormal oxidation of a low contact resistive WSix/WN diffusion barrier. The device with the plasma selective gate reoxidation showed superior gate oxide reliability and improved stress immunity of transistor compared to the thermally selective gate reoxidized devices

Oxidation behavior of a patterned TiSi2/polysilicon stack

The oxidation behavior at the sidewall of patterned TiSi2/polysilicon gate stack has been studied at temperatures from 700 to 850u200a°C. Oxidation above 800u200a°C caused an abnormally enhanced oxidation of TiSi2 sidewall, which was not observed in unpatterned TiSi2/polysilicon stack, regardless of the oxidation atmosphere. High-resolution transmission electron microscopy study showed that a SiO2–TiO2 mixture was produced during the enhanced oxidation of TiSi2 film. Lightly doped drain structures with TiSi2/polysilicon gate and nitride spacer were fabricated using gate reoxidation at 750u200a°C without degradation of sheet resistance.

Effects of thermal processes after silicidation on the performance of TiSi/sub 2//polysilicon gate device

The effects of thermal processes after silicidation on the gate depletion, threshold voltage (V/sub th/) shift, drive current, and sheet resistance of TiSi/sub 2//polysilicon (Ti-polycide) gate devices are evaluated. The dopant depletion of the polysilicon film, which is known to increase the V/sub th/ and to degrade the drive-current, increases with increasing temperature of the post-thermal process. However, the V/sub th/ roll-off characteristic in nMOSFETs is enhanced with increasing temperature. Furthermore, the drive-current is significantly degraded by the gate reoxidation process. The sheet resistance of the Ti-polycide gate increases with gate reoxidation as well as with increased post-thermal processes.

Roles of Ti, TiN, and WN as an Interdiffusion Barrier for Tungsten Dual Polygate Stack in Memory Devices

Tungsten dual polygate (W-DPG) stacks with diffusion barriers formed by the Ti(N) process were investigated in terms of gate contact resistance (Rc) and the polydepletion effect. The Ti layer in the Ti/WN diffusion barrier is found to be converted into a TiSix/TiN bilayer during the postdeposition annealing process. The TiSix reaction between Ti and p+ polycrystalline silicon (poly-Si) effectively prevents the formation of a parasitic dielectric layer, which could lead to low-gate Rc. The TiN reaction between Ti and WN minimizes the occurrence of the TiSix reaction, which effectively reduces p+ polydepletion caused by the out-diffusion of boron during the postdeposition annealing process. Therefore, poly-Si/Ti/WN/W could be a promising tungsten dual polygate stack, which satisfies high-speed requirements in dynamic random-access memory (DRAM) devices.

Gate Oxide Reliability Characterization of Tungsten Polymetal Gate with Low-Contact-Resistive WSix/WN Diffusion Barrier in Memory Devices

Gate oxide reliability characteristics using different diffusion barrier metals for a tungsten polycrystalline silicon (poly-Si) gate stack were investigated in detail. The insertion of a thin WSix layer in a tungsten poly gate stack could effectively relieve the mechanical stress of a gate hardmask nitride film during a post thermal process, which contributes to better gate oxide reliability and the stress-immunity of the transistor. This insertion could also prevent the formation of a Si–N inter-dielectric layer, which could lower the contact resistance between poly and tungsten effectively. A W/WN/WSix/poly gate stack could be a promising candidate for a future W poly gate that shows reliable high-speed characteristics in dynamic random access memory applications.

Impact of Thin WSIX Insertion in Tungsten Polymetal Gate on Gate Oxide Reliability and Gate Contact Resistance

By inserting thin WSix layer in tungsten poly gate stack we can effectively relieve the mechanical stress of gate hard mask nitride film, which contributes to the better gate oxide reliability and stress-immunity of transistor. This insertion also could prevent the formation of Si-N dielectric layer atop poly-Si, which could lower the contact resistance between poly and tungsten effectively

Control of the Slope of Field Oxide Edge and Its Effects on Gate Oxide Reliability

Effect of field oxidation ambients on the gate oxide reliability in recessed local oxidation of silicon (LOCOS) with a nitride spacer has been studied. Conventional wet ambient field oxidations produced negative field oxide edge slopes and resulted in gate oxide thinning at the field oxide edges, leading to degraded gate oxide characteristics. We have found that the slope of field oxide edge can be modified from negative to positive by oxidizing in a dry ambient or in a wet and subsequent dry ambient. No gate oxide thinning was observed when the edge slope was controlled to be positive. Considering field‐oxide‐ungrowth phenomenon, field oxide thinning effect, gate oxide thinning, and gate oxide reliability, a three‐step field oxidation method was proposed for the recessed LOCOS.

Effect of selective oxidation conditions on defect generation in gate oxide

With the shrinkage of memory devices below sub-100 nm technology, the gate electrode with low resistivity is more required to improve device speed. Tungsten/polysilicon (W/poly-Si) has been widely studied due to its low resistivity. One of the problems in the W/poly-Si gate is the oxidation of W during conventional gate reoxidation in O2 ambient after gate patterning. A selective oxidation (SO) process in H2-rich H2O ambient is considered to be the solution, where Si is selectively oxidized without the oxidation of W. 1) The incorporation of hydrogen into the device, however, has a strong effect on the electrical characteristics of the device. Annealing in hydrogen ambient is used for the passivation of silicon dangling bonds in Sibased devices. 2,3) The hydrogen introduced for the passivation of these defects is known to create defects in gate oxide during a device operation. The hydrogen released into the oxide by radiation or electrical stress generates interface states and subsequently degrades the electrical characteristics of the oxide such as enhanced hot carrier degradation and negative bias temperature instability. 4,5) High-temperature annealing in N2/H2 forming gas is also reported to generate mobile hydrogenous positive ions in the oxide which can be electrically driven across the oxide. 6–8) It is therefore expected that the gate oxide reliability in the W/ poly-Si/SiO2 is also degraded by the SO process. The effect of the SO process in H2-containing ambient has, however, not reported in detail. In this paper, we report the effect of the SO process on the degradation of gate oxide in terms of stress-induced leakage current (SILC), oxide trap density, and interface state density (Dit). 2. Experimental