Kwang Hwan Ji

Effect of high-pressure oxygen annealing on negative bias illumination stress-induced instability of InGaZnO thin film transistors

Negative-bias illumination stress (NBIS) of amorphous InGaZnO (IGZO) transistors can cause a large negative shift (>7.1 V) in threshold voltage, something frequently attributed to the trapping of photoinduced hole carriers. This work demonstrates that the deterioration of threshold voltage by NBIS can be strongly suppressed by high-pressure annealing under 10 atm O2 ambient. This improvement occurred through a reduction in oxygen vacancy defects in the IGZO film, indicating that a photoinduced transition from VO to VO2+ was responsible for the NBIS-induced instability.

Comparative Study on Light-Induced Bias Stress Instability of IGZO Transistors With

This letter examines the effect of the gate dielectric material on the light-induced bias-temperature instability of an In-Ga-Zn-O (IGZO) thin-film transistor (TFT). After applying positive and negative bias stresses, the SiNx-gated TFT exhibited inferior stability to the SiO2-gated TFT, which was explained by the charge trapping mechanism. However, light illumination under a negative bias stress accelerated the negative displacement of the threshold voltage (Vth) of the SiNx-gated IGZO TFT compared to that of the SiO2-gated TFT. This was attributed to the injection of photocreated hole carriers into the underlying gate dielectric bulk region as well as the hole trapping at the gate/channel interface.

\hbox{SiN}_{x}

We investigated the effect of device configuration on the light-induced negative bias thermal instability of gallium indium zinc oxide transistors. The V th of back-channel-etch (BCE)-type transistors shifted by ―3.5 V, and the subthreshold gate swing (SS) increased from 0.88 to 1.38 V/decade after negative bias illumination temperature stress for 3 h. However, etch-stopper-type devices exhibited small V th shifts of ―0.8 V without degradation in the SS value. It is believed that the inferior instability of the BCE device is associated with the formation of an interfacial molybdenum (Mo) oxychloride layer, which occurs in the course of dry etching Mo using Cl 2 /O 2 for source/drain patterning.

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The impact of a gate insulator (GI) material on the device instability of InGaZnO (IGZO) thin film transistors (TFTs) was investigated. The IGZO TFTs with SiO 2 GI showed consistently better stability against the applied temperature stress and positive/negative gate bias stress than their counterparts with SiN x GI. This superior stability of the SiO 2 -gated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities. Based on the Meyer-Neldel rule, the total DOS energy distribution for both devices was extracted and compared, which can explain the experimental observation.

\hbox{SiO}_{2}

This study examined the effect of the thickness of interfacial indium-tin oxide (ITO) on the performance and bias reliability of zinc-tin oxide (ZTO) thin film transistors (TFTs). The 3.5-nm-thick ITO-inserted ZTO TFTs exhibited superior mobility (43.2 cm2/V s) to that of the ZTO only TFTs (31.6 cm2/V s). Furthermore, the threshold voltage shifts for the ZTO/ITO bi-layer device decreased from 1.43 and −0.88 V (ZTO only device) to 0.46 V and −0.41 V under positive and negative bias stress, respectively. This improvement can be attributed to a decrease in the interfacial trap density for the ITO-inserted ZTO device.

Gate Dielectrics

This study examined the effect of oxygen (O2) high pressure annealing (HPA) on tin-doped indium oxide (ITO) thin film transistors (TFTs). The HPA-treated TFT at 150 °C exhibited a high saturation mobility (μSAT), low subthreshold gate swing (SS), threshold voltage, and Ion/off of 25.8 cm2/Vs, 0.14 V/decade, 0.6 V, and 2 × 108, respectively. In contrast, the ambient-annealed device suffered from a lower μSAT and high SS value of 5.2 cm2/Vs and 0.58 V/decade, respectively. This improvement can be attributed to the decreased concentration of oxygen vacancy defects in the ITO channel layer during the effective O2 HPA treatment, which also resulted in smaller hysteresis and less degradation of the drain current under positive bias stress conditions.

The Impact of Device Configuration on the Photon-Enhanced Negative Bias Thermal Instability of GaInZnO Thin Film Transistors

The optical absorption in the sub-gap region of amorphous indium zinc oxide films and the photo-induced negative bias stability of the resulting thin film transistors were studied. As the indium ratio increases, optical absorption via sub-gap states increases, and the threshold voltage degradation under negative bias temperature stress (NBTS) with light illumination becomes more severe. By applying high pressure anneal treatments in oxygen ambient, the density of sub-gap states is reduced by an order of magnitude compared to air-annealed devices. Consequently, significant improvements are observed in the threshold voltage shifts and the stretched exponential parameters under NBTS with light illumination.

The Effect of Density-of-State on the Temperature and Gate Bias-Induced Instability of InGaZnO Thin Film Transistors

We demonstrate that controlled cation composition in ITO-based films combined with solid-solution doping by titanium as well as the suppression of crystallization. The field-effect transistor having 3.7at% Ti-doped ITO film exhibited the high mobility of 13.4 cm2/Vs, low subthreshold gate swing of 0.25V/decade, and high Ion/off ratio of >108.

Improvement in both mobility and bias stability of ZnSnO transistors by inserting ultra-thin InSnO layer at the gate insulator/channel interface

We investigated the effect of gate dielectric structure on the light-induced bias-temperature instability of IGZO TFT. After the application of light-induced negative bias stress, the SiO<inf>2</inf>/SiN<inf>x</inf> bilayer gate dielectric TFT exhibited the superior stability than single layer gate dielectric TFTs. Total applied electric field to bilayer gate dielectric layer(Device C) is −1.91MV/cm. However, electric field applied bilayer gate dielectrics divided between SiN<inf>x</inf>(−0.76MV/cm) and SiO<inf>2</inf>(−1.15MV/cm). In case of SiO<inf>2</inf> single layer(Device A) effective electric field is −1.52MV/cm. This result indicates that bilayer gate dielectric structure has reducing electric field to gate dielectric. In addition, we observed different recovery behavior after negative bias temperature illumination stress. SiO<inf>2</inf>/SiN<inf>x</inf> bilayer TFT showed quickly recovery after stress as same as SiO<inf>2</inf> single layer gate dielectric. This results can be explained photo-created charge temporary trapping at the SiO<inf>2</inf>/active interface. On the other hand, photo-created charge deeply injection to SiN<inf>x</inf> gate dielectric as well as trapping at the gate dielectrics/active interface.