Kwangok Jeong

32nm 1-D Regular Pitch SRAM Bitcell Design for Interference-Assisted Lithography

As optical lithography advances into the 45nm technology node and beyond, new manufacturing-aware design requirements have emerged. We address layout design for interference-assisted lithography (IAL), a double exposure method that combines maskless interference lithography (IL) and projection lithography (PL); cf. hybrid optical maskless lithography (HOMA) in [2] and [3]. Since IL can generate dense but regular pitch patterns, a key challenge to deployment of IAL is the conversion of existing designs to regular-linewidth, regular-pitch layouts. In this paper, we propose new 1-D regular pitch SRAM bitcell layouts which are amenable to IAL. We evaluate the feasibility of our bitcell designs via lithography simulations and circuit simulations, and confirm that the proposed bitcells can be successfully printed by IAL and that their electrical characteristics are comparable to those of existing bitcells.

Impact of Guardband Reduction On Design Outcomes: A Quantitative Approach

The value of guardband reduction is a critical open issue for the semiconductor industry. For example, due to competitive pressure, foundries have started to incent the design of manufacturing-friendly ICs through reduced model guardbands when designers adopt layout restrictions. The industry also continuously weighs the economic viability of relaxing process variation limits in the technology roadmap (available: http://public.itrs.net). Our work gives the first-ever quantification of the impact of model guardband reduction on outcomes from the synthesis, place and route (SP&R) implementation flow. We assess the impact of model guardband reduction on various metrics of design cycle time and design quality, using open-source cores and production (specifically, ARM/TSMC) 90- and 65-nm libraries and technologies as well as an industrial embedded processor core implemented in 45 nm. Our experimental data clearly shows the potential design quality and turnaround time benefits of model guardband reduction. For example, in our open-source cores, on average we observe 13% standard-cell area reduction, 12% routed wirelength reduction, 13% dynamic power reduction and 19% leakage power reduction as the consequence of a 40% reduction in library model guardband; 40% is the amount of guardband reduction reported by IBM for a variation-aware timing methodology. For the embedded processor core we observe up to 8% standard-cell area reduction, 7% routed wirelength reduction, 5% dynamic power reduction, and 10% leakage power reduction at 30% guardband reduction. We also report a set of fine-grain SPICE simulations that accurately assesses the impact of process guardband reduction, as distinguished from overall guardband reductions, on yield. We observe up to 4% increase in number of good dies per wafer at 27% process guardband reduction (i.e., with fixed voltage and temperature). Our results suggest that there is justification for the design, EDA and process communities to enable guardband reduction as an economic incentive for manufacturing-friendly design practices.

Assessing chip-level impact of double patterning lithography

Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology options such as high refractive index materials, extreme ultraviolet (EUV), or e-beam lithography. DPL implements patterns on a single layer using either additional masks (e.g., double exposure or double patterning) or many additional processing steps (e.g., spacer double patterning). Overlay between the two layers introduces additional variability in both front-end-of-line (FEOL) and back-end-of-line (BEOL) by means of coupling capacitance variation. FEOL variability can be incorporated into standard characterization. However, the impacts of overlay in BEOL require new circuit analysis techniques. Furthermore, such techniques can guide technology developers toward DPL technology options that will have least variability impact on circuit performance. Today, the industry is nearing a critical juncture for choosing among various DPL technology options and process control capabilities. Accordingly, a rigorous, efficient framework is needed for variational performance analyses at chip level, and across many DPL technology options. Once a DPL method is chosen, a chip-level framework similar to what we present here will be required for circuit analysis and optimization. In this paper, we first analyze mechanisms of space and linewidth variation arising from overlay in various double patterning lithography options. We then develop a foundation of both TCAD-based and chiplevel methods, along with an effective design of experiments, to assess electrical impacts of BEOL variations. We conclude with an assessment of relative viabilities of DPL technology options under a range of process control scenarios.

Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography

Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes and prints the shapes of a critical-layer layout in two exposures. In traditional single-exposure lithography, adjacent identical layout features will have identical mean critical dimension (CD), and spatially correlated CD variations. However, with DPL, adjacent features can have distinct mean CDs, and uncorrelated CD variations. This introduces a new set of ‘bimodal’ challenges for timing analysis and optimization. We assess the potential impact of DPL on timing analysis error and guardbanding, and find that the traditional ‘unimodal’ characterization and analysis framework may not be viable for DPL. For example, using 45nm models, we find that different DPL mask layout solutions can cause 50ps skew in clock distribution that is unseen by traditional analyses. Different mask layouts can also result in 20% or more change in timing path delays. Such results lead to insights into physical design optimizations for clock and data path placement and mask coloring that can help mitigate the error and guardband costs of DPL.

Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography

Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32 nm node. DPL decomposes and prints the shapes of a critical-layer layout in two exposures. In traditional single-exposure lithography, adjacent identical layout features will have identical mean critical dimension (CD), and spatially correlated CD variations. However, with DPL, adjacent features can have distinct mean CDs, and uncorrelated CD variations. This introduces a new set of “bimodal” challenges for timing analysis and optimization. We assess the potential impact of bimodal CD distribution on timing analysis and guardbanding, and find that the traditional “unimodal” characterization and analysis framework may not be viable for DPL. We propose new bimodal-aware timing analysis and optimization methods to improve timing yield of standard-cell based designs that are manufactured using DPL. Our first contribution is a DPL-aware approach to timing modeling, based on detailed analysis of cell layouts. Our second contribution is an integer linear programming-based maximization of “alternate” mask coloring of instances in timing-critical paths, to minimize harmful covariance and performance variation. Third, we propose a dynamic programming-based detailed placement algorithm that solves mask coloring conflicts and can be used to ensure “double patterning correctness” after placement or even after detailed routing, while minimizing the displacement of timing-critical cells with manageable engineering change order (ECO) impact. With a 45 nm library and open-source design testcases, our timing-aware recoloring and placement optimization together achieve up to 271 ps (respectively, 55.75 ns) reduction in worst (respectively, total) negative slack, and 70% (respectively, 72%) reduction in worst (respectively, total) negative slack variation, respectively.

Quantified Impacts of Guardband Reduction on Design Process Outcomes

The value of guardband reduction is a critical open issue for the semiconductor industry. For example, due to competitive pressure, foundries have started to incent the design of manufacturing-friendly ICs through reduced model guardbands when designers adopt layout restrictions. The industry also continuously weighs the economic viability of relaxing process variation limits in the technology roadmap [2]. Our work gives the first-ever quantification of the impact of modeling guardband reduction on outcomes from the synthesis, place and route (SPR 40% is the amount of guardband reduction reported by IBM for a variation-aware timing methodology [8]. We also assess the impact of guardband reduction on design yield. Our results suggest that there is justification for the design, EDA and process communities to enable guardband reduction as an economic incentive for manufacturing-friendly design practices.

Is overlay error more important than interconnect variations in double patterning

Double patterning lithography seems to be a prominent choice for 32nm and 22nm technologies. Double patterning lithography techniques require additional masks for a single interconnect layer. Consequently, mask shift-induced overlay errors introduce additional variability into interconnect coupling capacitances. An important open question is whether overlay-induced performance impacts are more significant than performance variations caused by variability in interconnects. We provide TCAD as well as chip-level analyses to determine whether overlay error should receive more attention than interconnect variations during interconnect manufacturing. We develop conclusions to help determine which component should be given more importance in specific double patterning process variants.

Interference Assisted Lithography for Patterning of 1D Gridded Design

We present Interference Assisted Lithography (IAL) as a promising and cost-effective solution for extending lithography. IAL achieves a final pattern by combining an interference exposure with a trim exposure. The implementation of IAL requires that todays 2D random layouts be converted to highly regular 1D gridded designs. We show that an IAL-friendly 6T SRAM bitcell can be designed following 1D gridded design rules and that the electrical characteristics is comparable to todays 2D design. Lithography simulations confirm that the proposed bitcell can be successfully imaged with IAL.

Methodology from chaos in IC implementation

Algorithms and tools used for IC implementation do not show deterministic and predictable behaviors with input parameter changes. Due to suboptimality and inaccuracy of underlying heuristics and models in EDA tools, overdesign using tighter constraints does not always result in better final design quality. Moreover, negligibly small input parameter changes can result in substantially different design outcomes. In this paper, we assess the nature of ‘chaotic’ behavior in IC implementation tools via experimental analyses, and we determine a methodology to exploit such behavior based on the ‘multi-run’ and ‘multi-start’ sampling concepts proposed in [2]. We also suggest the number of sampling trials that yields more predictably good solutions; this allows us to improve quality of design without any manual analysis or manipulation, without changing any existing tool flows, and without unnecessary expenditure of valuable computing resources.

Accurate Machine-Learning-Based On-Chip Router Modeling

As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power, performance, and area has become crucially important. In this work, we develop accurate architecture-level on-chip router cost models using machine-learning-based regression techniques. Compared against existing models (e.g., ORION 2.0 and parametric models), our models reduce estimation error by up to 89% on average.