Kwisung Yoo

Code-width testing-based compact ADC BIST circuit

This paper proposes a new analog-to-digital converter (ADC) built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal. The proposed BIST scheme can be implemented by a simple digital circuit whose gate count is only approximately 550. The proposed BIST scheme is verified by simulation with 138 test circuits of 6-b pipeline ADC with arbitrary faults. Simulation results show that it effectively detects not only the catastrophic faults but also some parametric faults. The simulated fault coverage is approximately 99%.

CMOS image sensor with analog gamma correction using nonlinear single-slope ADC

A human eye has the logarithmic response over wide range of light intensity. Although the gain can be set high to identify details in darker area on the image, this results in saturation in brighter area. The gamma correction is essential to fit the human eye. However, the digital gamma correction degrades image quality especially for darker area on the image due to the limited ADC resolution and the dynamic range. This paper proposes a CMOS image sensor (CIS) with nonlinear analog-to-digital converter (ADC) which performs analog gamma correction. The CIS with the proposed nonlinear ADC conversion scheme was fabricated with a 0.35-mum CMOS process. The test results show the improved image quality than digital gamma correction

A Low-Power Gigabit CMOS Limiting Amplifier Using Negative Impedance Compensation and Its Application

This paper presents a low-power, gigabit limiting amplifier (LA) for application to optical receivers that employ the negative impedance compensation technique not only to enhance the gain and bandwidth characteristics simultaneously, but also to allow low-voltage, low-power operations. Test chips of the LA were implemented in a standard 0.18-μ m CMOS process, demonstrating 2.5-Gb/s operation with 40-dB gain, 0.053-UI rms jitter for 231-1 pseudorandom bit sequence inputs, 9.5-mVpp input sensitivity for 10-12 bit error rate (BER), and 5.2-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of only 0.25 × 0.1 mm2 . The proposed LA was adopted to realize a low-power, gigabit optical receiver. Fabricated using the same 0.18-μm CMOS technology, the measured results of the optical receiver chip reveal 132.6-dB Ω transimpedance gain, 2.7-GHz bandwidth even with a large 1.5-pF input parasitic capacitance, -16-dBm optical sensitivity for 10-12 BER, and 51-mW power dissipation from a single 1.8-V supply. The area of the whole chip is 1.75 × 0.45 mm2.

An adaptation method for FIR pre-emphasis filter on backplane channel

Ultra high-speed data transmission on a backplane suffers from inter-symbol interference (ISI), which degrades bit error rate (BER) performance. In order to reduce ISI, an adaptive equalizer or a pre-emphasis filter is placed on either a receiver or a transmitter side. Although adaptation methods for an equalizer have been introduced, those for a pre-emphasis filter have scarcely been reported. This paper proposes a structure of an adaptive pre-emphasis filter and its adaptation method to have optimal coefficients corresponding to channel

A low power CMOS adaptive line equalizer for fast Ethernet

An analog adaptive line equalizer has been developed for 155 Mbps fast Ethernet data communication up to 100 m UTP (unshielded twisted pair) cable. The proposed adaptive equalizer is designed for the 0.35 /spl mu/m CMOS process. The designed equalizer has low power consumption (19 mW) and small silicon area (0.07 mm/sup 2/).

A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in 0.18μm CMOS Using Negative-Impedance Compensation

A 2.5Gb/s limiting amplifier is realized in a standard 0.18μm CMOS process, exploiting the negative-impedance compensation technique. Measurements show 2.5Gb/s operation (0.5pF ESD protection diodes included) with 40dB gain, 21ps_rms jitter for 2³¹-1 PRBS, 9.5mV_pp input sensitivity with BER <10^-12, and 5.2mW power dissipation from a 1.2V supply. The chip core occupies 0.25×0.1mm².

Convergence analysis of the cascade second-order adaptive line equalizer

The high-speed data transmission on a twisted pair cable suffers from frequency-dependent loss that causes significant inter-symbol interference. Although a first-order adaptive equalizer based on pole-zero cancellation is sufficient to compensate the limited bandwidth for relatively low data rate, a higher order equalizer is necessary for higher data rate. This brief proposes a cascade second-order adaptive equalizer structure and provides its convergence analysis

A 5.2-mW, 2.5-Gb/s Limiting Amplifer for OC-48 SONET Applications

In this paper, a fully differential CMOS limiting amplifier is presented for OC-48 SONET applications. With negative resistance and capacitance characteristics, it achieves significant gain and bandwidth enhancement. The amplifier was implemented in a 0.18-mum CMOS process, occupying the chip area of 0.025 mm2. Post-layout simulation results demonstrate the bandwidth of 2.4-GHz, the differential gain of 41-dB, the input sensitivity of 1.5 mVpp, and the power consumption of only 5.2 mW from a single 1.2-V power supply.