Dongmyung Lee

A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture

Over the last few years, the demands for high-density and high-speed imaging have increased drastically. Since CMOS image sensors have the advantages of low power consumption and easy system integration, they have become dominant over CCDs in the consumer market [1–4]. A column-parallel ADC architecture is the most widely used ADC in CMOS image sensors for high-speed and low-power operation [2–6]. The column-parallel architecture can be classified as: successive-approximation register (SAR) [2], cyclic [3], single-slope (SS) [4], and delta-sigma (ΔΣ) [5,6] ADCs. Although SAR ADCs have been utilized for high-speed imaging, such as UDTV, they require a DAC in a column, whose area is unacceptably large for consumer electronics with a fine pixel pitch. Cyclic ADCs have also been reported in high-speed imaging, but they have high power consumption and high noise levels. Since SS ADCs provide relatively high resolution with minimum area, they have been widely used in CMOS image sensors. However, SS ADCs require very fast clock signals leading to high power consumption in the case of high-speed imaging. Although ΔΣ ADCs have been investigated for low-noise imaging, they have only been applied for low-speed imaging with large pixel pitch because of the complexity of ΔΣ modulators and following decimation filters.

An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer

An 8.5-Gb/s single-chip optoelectronic integrated circuit (OEIC) for short-distance optical communications is realized in a 0.13-μm CMOS process. The OEIC consists of an on-chip silicon photodiode, a transimpedance amplifier with modified regulated cascode input configuration, an adaptive equalizer based upon slope-detection algorithm, and a limiting amplifier with merged negative impedance circuits. The proposed slope-detection adaptive equalizer compensates the limited bandwidth and the temperature variation of the integrated silicon photodiode. Measured results demonstrate 120-dB Ω transimpedance gain, 5.9-GHz bandwidth, -3.2-dBm optical sensitivity for 10-12 BER, and 47-mW power dissipation from a single 1.5-V supply. The OEIC chip core occupies the area of 0.1 mm2.

Code-width testing-based compact ADC BIST circuit

This paper proposes a new analog-to-digital converter (ADC) built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal. The proposed BIST scheme can be implemented by a simple digital circuit whose gate count is only approximately 550. The proposed BIST scheme is verified by simulation with 138 test circuits of 6-b pipeline ADC with arbitrary faults. Simulation results show that it effectively detects not only the catastrophic faults but also some parametric faults. The simulated fault coverage is approximately 99%.

Low-Noise In-Pixel Comparing Active Pixel Sensor Using Column-Level Single-Slope ADC

A conventional active pixel sensor (APS) uses a source follower (SF) in a pixel as a buffer. This SF is one of the major causes of nonlinearity, sensitivity degradation, and pixel readout noise. The proposed in-pixel comparing APS uses pixel transistors as a part of comparator for a single-slope ADC instead of using them as an SF. The prototype sensor was fabricated using a 0.35-mum 2P3M CMOS process. Experimental results show 15-times linearity improvement, 26% sensitivity enhancement, and 33% noise reduction over the conventional APS.

A 20-Gb/s Transformer-Based Current-Mode Optical Receiver in 0.13-

A 20-Gb/s current-mode optical receiver is realized in a 0.13-μm CMOS process, which consists of a common-gate transimpedance amplifier (TIA) with on-chip transformers, a six-stage postamplifier (PA) with an offset cancellation network, and an output buffer. The transformer-based inductive peaking technique is exploited in the TIA to isolate the parasitic capacitances at high-impedance nodes and, hence, to enlarge the bandwidth. The PA incorporates source degeneration and interleaving active feedback techniques to achieve wide bandwidth and flat frequency response so as not to degrade the operation speed of the whole optical receiver. Measured results demonstrate 60-dbΩ transimpedance gain, 12.6-GHz bandwidth even with 0.4-pF large input parasitic capacitance, ߝ13-dBm sensitivity for a 10-12 bit error rate, and 38.3-mW power consumption from a single 1.2-V supply.

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This paper proposes a sub-1-V CMOS image sensor using a time-based readout (TBR) circuit. The proposed TBR circuit senses the moment of event from the pixel instead of reading the voltage signal. This allows the use of low power-supply voltage in pixel, providing sufficient dynamic range. The prototype chip was fabricated with a 0.13- ¿m standard CMOS logic process, and whole circuits were designed with thin-oxide gate transistors only. The measurement results show a 54.2-dB dynamic range with 0.75-V power-supply voltage.

CMOS

This paper presents a low-power, gigabit limiting amplifier (LA) for application to optical receivers that employ the negative impedance compensation technique not only to enhance the gain and bandwidth characteristics simultaneously, but also to allow low-voltage, low-power operations. Test chips of the LA were implemented in a standard 0.18-μ m CMOS process, demonstrating 2.5-Gb/s operation with 40-dB gain, 0.053-UI rms jitter for 231-1 pseudorandom bit sequence inputs, 9.5-mVpp input sensitivity for 10-12 bit error rate (BER), and 5.2-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of only 0.25 × 0.1 mm2 . The proposed LA was adopted to realize a low-power, gigabit optical receiver. Fabricated using the same 0.18-μm CMOS technology, the measured results of the optical receiver chip reveal 132.6-dB Ω transimpedance gain, 2.7-GHz bandwidth even with a large 1.5-pF input parasitic capacitance, -16-dBm optical sensitivity for 10-12 BER, and 51-mW power dissipation from a single 1.8-V supply. The area of the whole chip is 1.75 × 0.45 mm2.

Sub-1-V CMOS Image Sensor Using Time-Based Readout Circuit

Recently, low-cost silicon optoelectronic integrated circuits (OEICs) have been drawing attention for applications in short-distance optical communications such as chip-to-chip and board-to-board interconnects, LAN, data storage networks, etc [1–4]. Particularly, single-chip OEICs with on-chip silicon photodiodes provide a number of advantages including low cost, reduced ground-bounce, and bond-wire-induced coupling. Nevertheless, the slow response of silicon photodiodes in a standard CMOS process serves as a major bottleneck for high-speed communication [1]. To improve the bandwidth of silicon photodiodes, either some process modification or avalanche photodiode implementation has been developed. However, the former results in increased costs, whereas the latter has reliability issues. Although a differential photodiode configuration was originally proposed for bandwidth extension [2–4], the operation speed is still limited to several-hundred Mb/s. Meanwhile, the bandwidth can be extended by exploiting equalization filter [1, 3]. For relatively low-Gb/s operations, fixed equalization filter is sufficient, because photodiode responsivity is dominantly determined by diffusion currents which are not sensitive to process and temperature variations. For higher speeds, the responsivity becomes strongly dependent on the process and temperature variations, because it is mainly determined by the carrier mobility. Thereby, equalizers for high-Gb/s optical receivers require an adaptation algorithm to compensate the significant process and temperature variations. In this paper, an OEIC with on-chip photodiode is presented. Bandwidth and responsivity are compensated by a compact adaptive equalizer, thus achieving 8.5Gb/s operation.

A Low-Power Gigabit CMOS Limiting Amplifier Using Negative Impedance Compensation and Its Application

A without increasing steady bias current, realizing a switched capacitor amplifier circuit together to enable fast settling time characteristic rise and fall of the output signal. The apparatus includes input transistors M1 and amplifier 1 having a load transistor M2, a feedback capacitance CF1 first terminal connected to the amplifier input Ain, a switch SW1 provided between the amplifier input and output, a feedback capacitor CF1 the input signal voltage Vin 2 terminal with sampling period, the switched-capacitor circuit of the switch SW2 to connect the amplifier output Aout in the read period and the basic structure, further between the gate of the second terminal and the load transistor M2 of the feedback capacitance CF1 the second provided with a feedback capacitance CF2 for, a switch SW3 to cut during readout gate bias circuit 2 of the load transistor M2 to. .FIELD 1

An 8.5Gb/s CMOS OEIC with on-chip photodiode for short-distance optical communications

This paper proposes a high-speed single-chip eye tracker that eliminates the effect of the glint and generates the digital address for the center of the pupil.