Kyeong Ju Moon

ZnO single nanowire-based UV detectors

In this report, ZnO single nanowire (NW)-based devices were fabricated on the same nanowire by e-beam lithography so that both sides had Ohmic contact and one side had Schottky contact. Information about the mechanism for low-power UV detection by these devices was unambiguously provided by I-V measurements. Adsorption and desorption of oxygen molecules at the NW surface are responsible for the UV detection by the device with Ohmic contacts on both sides. Barrier height modulations and interface states are responsible for UV detection by the device with Schottky contact on one side.

Junction properties of Au/ZnO single nanowire Schottky diode

In this study, we have analyzed the Au/ZnO single nanowire based Schottky diode by investigating temperature dependent current voltage and x-ray photoelectron spectroscopy (XPS) measurements. The calculated barrier height of the Schottky diodes by using the thermionic emission model is in good agreement with the value obtained from the XPS measurements but lower than the theoretically predicted value. The ionization of interface states has been considered for explaining this discrepancy.

Effects of solution temperature on solution-processed high-performance metal oxide thin-film transistors

Herein, we report a novel and easy strategy for fabricating solution-processed metal oxide thin-film transistors by controlling the dielectric constant of H2O through manipulation of the metal precursor solution temperature. As a result, indium zinc oxide (IZO) thin-film transistors (TFTs) fabricated from IZO solution at 4 °C can be operated after annealing at low temperatures (∼250 °C). In contrast, IZO TFTs fabricated from IZO solutions at 25 and 60 °C must be annealed at 275 and 300 °C, respectively. We also found that IZO TFTs fabricated from the IZO precursor solution at 4 °C had the highest mobility of 12.65 cm2/(V s), whereas the IZO TFTs fabricated from IZO precursor solutions at 25 and 60 °C had field-effect mobility of 5.39 and 4.51 cm2/(V s), respectively, after annealing at 350 °C. When the IZO precursor solution is at 4 °C, metal cations such as indium (In3+) and zinc ions (Zn2+) can be fully surrounded by H2O molecules, because of the higher dielectric constant of H2O at lower temperatures. These chemical complexes in the IZO precursor solution at 4 °C are advantageous for thermal hydrolysis and condensation reactions yielding a metal oxide lattice, because of their high potential energies. The IZO TFTs fabricated from the IZO precursor solution at 4 °C had the highest mobility because of the formation of many metal-oxygen-metal (M-O-M) bonds under these conditions. In these bonds, the ns-orbitals of the metal cations overlap each other and form electron conduction pathways. Thus, the formation of a high proportion of M-O-M bonds in the IZO thin films is advantageous for electron conduction, because oxide lattices allow electrons to travel easily through the IZO.

Programmable Direct-Printing Nanowire Electronic Components

In order for recently developed advanced nanowire (NW) devices(1-5) to be produced on a large scale, high integration of the separately fabricated nanoscale devices into intentionally organized systems is indispensible. We suggest a unique fabrication route for semiconductor NW electronics. This route provides a high yield and a large degree of freedom positioning the device on the substrate. Hence, we can achieve not only a uniform performance of Si NW devices with high fabrication yields, suppressing device-to-device variation, but also programmable integration of the NWs. Here, keeping pace with recent progress of direct-writing circuitry,(6-8) we show the flexibility of our approach through the individual integrating, along with the three predesigned N-shaped sites. On each predesigned site, nine bottom gate p-type Si NW field-effect transistors classified according to their on-current level are programmably integrated.

Intrinsic memory behavior of rough silicon nanowires and enhancement via facile Ag NPs decoration

In inorganic nanowire memory, both physical features rendered during synthesis and integration processes and intrinsic properties of materials are important because they present appropriate schemes for facile fabrication of an excellent memory device. We demonstrate that silicon nanowires (Si NWs) synthesized by an electroless etching (EE) method intrinsically present memory behavior via charge trapping of water molecules due to the rough surface created during synthesis. Additionally, using an electrochemical reaction of silicon with AgNO3 solution, which produces Ag nanoparticles (NPs) with a blocking SiO2 layer, we easily achieve a Ag NP hybrid Si NW memory device.

A route for modulating the diameter of cylindrical silicon nanowires by using thermal self-ordering silver nanoparticles.

For the synthesis of uniform sub-80-nm silicon nanowires (Si NWs), we introduce a metal-assisted chemical etching (MCE)-based facile and high-yield route, employing simple thermal annealing and vacuum deposition processes. Under rapid thermal annealing, an ultrathin silver (Ag) film on a Si substrate is self-organized into Ag nanoparticles (NPs), which are used for making Si nanoholes through a short MCE process. After sputter deposition of Au (10 nm)/Ag (20 nm) on the caved Si substrate with nanoholes, a nanomesh is obtained. Finally, with the nanomesh as an etching mask, Si NWs are successfully produced through a second MCE process. The size of the Si NWs can be modulated by controlling the thickness of the initial Ag film. The minimum diameter of the synthesized Si NWs is 30 ± 5 nm, and the maximum diameter is 68 ± 10 nm. Furthermore, to determine the uniformity of our Si NWs, bottom-gate field-effect transistors were fabricated and the linearity of the on-current level of these transistors with the number of addressed Si NWs was confirmed.

One-Dimensional Semiconductor Nanostructure Based Thin-Film Partial Composite Formed by Transfer Implantation for High-Performance Flexible and Printable Electronics at Low Temperature

Having high bending stability and effective gate coupling, the one-dimensional semiconductor nanostructures (ODSNs)-based thin-film partial composite was demonstrated, and its feasibility was confirmed through fabricating the Si NW thin-film partial composite on the poly(4-vinylphenol) (PVP) layer, obtaining uniform and high-performance flexible field-effect transistors (FETs). With the thin-film partial composite optimized by controlling the key steps consisting of the two-dimensional random dispersion on the hydrophilic substrate of ODSNs and the pressure-induced transfer implantation of them into the uncured thin dielectric polymer layer, the multinanowire (NW) FET devices were simply fabricated. As the NW density increases, the on-current of NW FETs increases linearly, implying that uniform NW distribution can be obtained with random directions over the entire region of the substrate despite the simplicity of the drop-casting method. The implantation of NWs by mechanical transfer printing onto the PVP layer enhanced the gate coupling and bending stability. As a result, the enhancements of the field-effect mobility and subthreshold swing and the stable device operation up to a 2.5 mm radius bending situation were achieved without an additional top passivation.

White light emission from heterojunction diodes based on surface-oxidized porous Si nanowire arrays and amorphous In-Ga-Zn-O capping.

A novel heterojunction white light emitting diode (LED) structure based on an array of vertically aligned surface-passivated p-type porous Si nanowires (PSiNWs) with n-type amorphous In-Ga-Zn-O (a-IGZO) capping is introduced. PSiNWs were initially synthesized by electroless etching of p-type Si (100) wafers assisted by Ag nanoparticle catalysts and then surface-passivated by thermal oxidation. The nanowires synthesized by metal-assisted electroless etching were found to have longitudinally varying nanoporous morphologies due to differences in the duration of exposure to etching environment. These PSiNWs were optically active with orange red photoluminescence consisting of dark red to yellow emissions attributable to quantum confinement effects and to modified band structures. The LED structures emitted visible white light while exhibiting rectifying current-voltage characteristics. The white light emission was found to be the result of the combination of dark red to yellow emissions originating from the quantum confinement effect within the PSiNWs and green to blue emissions due to the oxygen-deficiency-related recombination centers introduced during the surface oxidation.

Logic inverters based on the property modulated Si nanowires by controlled surface modifications

Silicon nanowires (Si NWs) showing stabilized n-type conductivity, which can be fabricated with high yield by simple surface treatment, are presented in this study. Si NWs were initially fabricated by electroless etching of phosphine-doped n-type Si wafers. At this stage, Si NWs showed large scatter in electrical properties. Once these nanowires were post-annealed in oxidizing ambient and then wet-etched in dilute HF solution, their electrical properties were markedly improved and stabilized to show proper n-type conductivity. Microstructural examination revealed that such improvements and stabilization accompanied flattening of the outer surface and removal of surface defects due to the surface treatment processes. To demonstrate the applicability of these n-type Si NWs to logic devices, a model complementary metal–oxide–semiconductor (CMOS) was prepared by transfer implantation of p- and n-type Si NWs on a poly(4-vinylphenol) layer and this model CMOS showed logic inverter characteristic with controllable gain.

A simple and rapid formation of wet chemical etched silicon nanowire films at the air-water interface

A spontaneous assembly route to form a thin film of nanowires (NWs) was demonstrated and its feasibility was confirmed through the fabrication of a high-performance multi-Si NW field effect transistor (FET) using this route. Governed by the three mechanisms of spreading, trapping, and two-dimensional packing, the route was optimized for the concentration of Si NWs and the initial volume ratio of aqueous hydrochloride solution to isopropyl alcohol. The successfully formed Si NW thin-film was transferred on a flat polydimethylsiloxane (PDMS) mold and regulated using a repeatable conformal contact method with a new flat PDMS to prepare it for decal printing on an organic dielectric layer. Finally, after depositing the source and drain electrodes on the printed active layer, a high-performance 23-bridged Si NW FET exhibiting a μeff of 51.4 cm2 V−1s−1, an on/off drain current ratio of 105, and a Vth of −2.7 V was obtained.