Woong Lee

Fully 3-Dimensional NOR Flash Cell with Recessed Channel and Cylindrical Floating Gate - A Scaling Direction for 65nm and Beyond

For the first time, a fully 3-dimensional (3-D) flash cell with recessed channel and cylindrical floating gate is successfully integrated with 65nm MLC NOR flash technology. Key process technologies to achieve the novel cell structures are shown to be highly feasible. Superior scalability and comparable device characteristics including V th distribution and tunnel oxide reliability are proved through 512Mb full chip integration. Intrinsic immunity on the short channel effect of this 3-D cell opens a promising path for the continued scaling of the floating gate flash memories for 65nm and beyond

Development and Optimization of Re-Oxidized Tunnel Oxide with Nitrogen Incorporation for the Flash Memory Applications

The reliability properties of NOR flash memory with 65nm node being developed in Samsung electronics are greatly improved by using the newly proposed re-oxidized tunnel oxide. Especially, by optimizing the process variables such as the re-oxidation thickness/time, the partial pressure of NO during annealing, and the kinds of re-oxidizing materials, the Vth shifts post cycling and after post-cycling bake were decreased to the level of 28% and 42% of conventional NO annealed tunnel oxide, respectively.

Effect of STI shape and tunneling oxide thinning on cell Vth variation in the flash memory

We studied factors which affect cell Vth variation in the floating gate flash memory. By simulation and experiment, we showed that the shape of STI (shallow trench isolation) and the tunnel oxide thickness in the STI edge were the main control factors. For example, sharp and thin oxide in the STI edge caused an uncontrolled F-N gate current in the program or erase operation, which directly indicated the amount of threshold voltage in the flash memory. Furthermore, we found that tunnel oxide thinning was closely related to the activation energy in the oxidation process. Smaller activation energy resulted in better thinning and better cell Vth distribution.

Leakage current reduction mechanism of oxide-nitride-oxide inter-poly dielectrics through the post plasma oxidation treatment

High quality oxide–nitride–oxide (ONO) inter-poly dielectrics were successfully fabricated by the optimized plasma oxidation without H2. The bottom low pressure chemical vapor deposition (LPCVD) oxides treated by the conventional N2O annealing step were subjected to the post deposition process using a plasma treatment. This process reduces both the leakage current and the stress-induced leakage current (SILC), while no thickness increase of the bottom LPCVD oxides was observed due to the plasma treatment. Based on the photo electron injection technique, it is found that the O2 plasma oxidation method significantly reduces the defect centers located at 1.67 nm away from the bottom oxide/floating gate interface.

A 90nm generation NOR flash multilevel cell (MLC) with 0.44/spl mu/m/sup 2//bit cell size

A 256Mb NOR MLC flash memory with 90nm technology has been successfully developed. Through judicious integration to control the cell dispersion and charge loss/gain with cycling, we confirm a successful MLC operation up to 10K cycling for 0.44 /spl mu/m/sup 2//bit cell size. In this paper, the key features governing multilevel cell (MLC) operation below 90nm technology node is discussed with experimental results.