Kyeong-Yuk Min

A hybrid image coding in overdriving for motion blur reduction in LCD

Overdriving technique enlarges the desired change of the pixel value, the error in general compression methods is enlarged at the same time. Therefore, we propose a novel Adaptive Quantization Coding (AQC) to reduce the error in compression for overdriving technique reducing motion blur. Considering hardware implementation, we develop a hybrid image coding which uses color transform first, and then uses AQC to compress luminance data as well as Block Truncation Coding (BTC) to compress chrominance data. The simulation results shown that the average PSNR was improved 5.676dB as compared with the result of BTC, and the average SD of error was reduced 50.2% than that in the BTC. The proposed algorithm is implemented with the verilog HDL and synthesized with the synopsys design compiler using 0.13µm Samsung Library.

A Memory and Performance Optimized Architecture of Deblocking Filter in H.264/AVC

In this paper, we propose memory and performance optimized architecture to accelerate the operation speed of adaptive deblocking filter for H.264/JVT/AVC video coding. The proposed deblocking filter executes loading/storing and filtering operations with only 232 cycles for 1 macroblock. Only 2 times 4 times 4 internal buffers and 32 times 16 internal SRAM are adopted for the buffering operation of deblocking filter with I/O bandwidth of 32 bit. The proposed architecture can process the filtering operation for 1 macroblock with less filtering cycles and lower memory sizes than some conventional approaches of realizing deblocking filter. The efficient hardware architecture is implemented with novel data arrangement, hybrid filter scheduling and minimum number of buffer. The proposed architecture is suitable for low cost and real-time applications, and the real-time decoding with 1080HD (1920 times 1088 @ 30fps) can be easily achieved when working frequency is 85.2MHz.

A memory-efficient VLC decoder architecture for MPEG-2 application

Video data compression is a major key technology in the field of multimedia applications. Variable-length coding is the most popular data compression technique which has been used in many data compression standards, such as JPEG, MPEG and image data compression standards, etc. We present a memory-efficient VLC decoder architecture for MPEG-2 application which can achieve small memory space and higher throughput. To reduce the memory size, we propose a new grouping, remainder generation method and merged lookup table (LUT) for variable length decoders (VLDs). In the MPEG-2, the discrete cosine transform (DCT) coefficient table zero and one are mapped onto one memory whose space requirement has been minimized by using efficient memory mapping strategy. The proposed memory size is only 256 words in spite of mapping two DCT coefficient tables.

A real-time JPEG encoder for 1.3 mega pixel CMOS image sensor SoC

In this paper, we propose a hardware architecture of low-power and real-time JPEG encoder for 1.3 mega pixels CMOS image sensor SoC which can be applied to mobile communication devices. The proposed architecture has an efficient interface scheme with CMOS image sensor and other peripherals for real-time encoding. The JPEG encoder supports the base-line JPEG mode, and processes motion images of which resolution is up to 1280/spl times/960 (CCIR601 YCrCb 4:2:2,15 fps) by real-time processing. The JPEG encoder supports 8 types of resolution, and can serve the 4 levels of image quality through quantization matrix. The proposed JPEG encoder can transfer encoded motion pictures and raw image data from CMOS image sensor to external device through USB 2.0 and a compressed still image is stored at external pseudo SRAM through SRAM interface. And proposed core can communicate parameters of encoding type with other host by I2C. The proposed architecture was implemented with VHDL and verified for the functions with Synopsys and Modelsim. The encoder proposed in this paper was fabricated in process of 0.18u of Hynix semiconductor Inc.

Improved BTC Using Luminance Bitmap for Color Image Compression

Block truncation coding (BTC) is an efficient technology for color image compression. An improved BTC algorithm, luminance bit-map based BTC (LBBBTC), is presented in this paper. The LBB-BTC employs luminance bit-map to represent the three R, G and B bit-maps more exactly. Moreover, by adding 3 bits to indicate the entirely differences between Y and R, G or B bit-maps, respectively, the coding performance is improved obviously. Simulation results show that the proposed LBB-BTC performs as well as the BTC in terms of subject visual quality and PSNR, and significantly improve the compression ratio of BTC.

An efficient VLSI architecture for full-search variable block size motion estimation in H.264/AVC

In this paper, an efficient VLSI architecture of full-search variable block size motion estimation (VBSME) suitable for high quality video is proposed. Memory bandwidth in high-quality video is a mainly responsible for throughput limitations and power consumption in VBSME. The proposed architecture is designed for reducing the memory bandwidth by adopting “meander”-like scan for a high overlapped data of the search area and using on-chip memory to reuse the overlapped data. We can reuse the previous candidate block of 98% for the current one and save memory access cycles about 19% in a search range of [-32, +31]. The architecture has been prototyped in Verilog HDL and synthesized by Synopsys Design Compiler with Samsung 0.18um standard cell library. Under a clock frequency of 67MHz, The simulation result shows that the architecture can achieve the real-time processing of 720x576 picture size at 30fps with the search range of [-32~+31].

An efficient architecture of deblocking filter with high frame rate for H.264/AVC

In this paper, we propose an efficient hardware architecture of the deblocking filter for H.264/JVT/AVC. Earlier designs have demerit of long processing time, since the reading, writing and filtering operations have been processed in each cycles. This paper proposes a new architecture that enables filtering of vertical edge concurrent with data loading as well as filtering of horizontal edge concurrent with writing to the external memory. The experimental result shows that the necessary cycle for filtering can be reduced by 38% in comparison with the conventional method and the new architecture has advantage in power consumption.

A pentagonal fast block matching algorithm for motion estimation using adaptive search range

In this paper, we present a PFBMA (pentagonal fast block matching algorithm) using adaptive search range. The proposed algorithm classifies images into dynamic and static images by a motion equation and performs block matching using adaptive search range. The motion equation calculates the degree of motion in a MB (macro block). A MB declared as static by this equation is matched with a small fixed search range and a MB declared as dynamic is estimated with three different search ranges. In this search pattern, more points are allocated in the region of high MV (motion vector) probability which is found by smaller matching error and these searching points appear like a pentagonal shape. This proposed pentagonal search pattern also considers search direction to avoid a local minimum. The experimental results show that the proposed algorithm achieves low computational complexity and better image quality compared with other conventional fast block matching algorithms.

Low-cost implementation of bird's-eye view system for camera-on-vehicle

Many papers concentrate on the 3*3 perspective transformation matrix calculation of birds view system, but few discussed for the whole system implementation. In this paper, a low-cost birds-eye view system is proposed, which adopts an elaborate software/hardware cooperative system structure. It can be applied to all kinds of vision-based system in vehicles directly as a ready-made module.

The new memory-efficient hardware architecture of CAVLD in H.264/AVC for mobile system

In this paper, we propose a new Context-based Adaptive Variable Decoding (CAVLD) hardware architecture without memory fabrication for mobile process. Previous CAVLD hardware architecture consists of five step blocks and each block gets several bits from controller and Look-Up Tables (LUTs). Many researches on LUTs basically require Read Only Memory (ROM) or Random Access Memory (RAM) fabrication process which is difficult to be implemented in general mobile digital logic fabrication process. In this reason, the hardware architecture for CAVLD inevitably has large hardware area and high power consumption. This paper propose two techniques, which combines five steps into four steps and optimizes LUTs without embedded memory for reducing chip size. By adopting these two techniques, the memory size is reduced 15% and the processing time is reduced 33% compared with previous architectures.