Jong-Wha Chong

A study of joint tracking algorithms of carrier frequency offset and sampling clock offset for OFDM-based WLANs

We present three joint tracking algorithms of carrier frequency and sampling clock offsets for OFDM-based WLAN systems, such as IEEE 802.11a standard. In such systems, one symbol usually contains a few pilots so that the estimation accuracy and robustness of conventional methods do not satisfy the system requirement. In this paper, three joint tracking algorithms for accurate frequency and sampling estimation are presented. The first method is performed by a one-dimensional least square estimation and averaging over L symbols. The second algorithm compares the phase difference of the current symbol with the subsequent D-th symbol and gives better performance, especially when the SNR or synchronization offset is smaller. The third method uses two-dimensional linear least square estimation within the frequency and time domains. Simulations using these algorithms have been performed with 16-QAM modulation schemes. Simulation results show that the three algorithms can improve the estimation accuracy and robustness.

Development of a miniature scintillation camera using an NaI(Tl) scintillator and PSPMT for scintimammography

We have developed a small scintillation camera dedicated to breast imaging and have evaluated the performance of the system. In order to increase the limited field of view (FOV) determined by the size of a position-sensitive photomultiplier tube (PSPMT), the imaging characteristics of a diverging hole collimator (DHC) were also investigated. The small scintillation camera system consists of an NaI(Tl) crystal (60 mm x 60 mm x 6 mm) coupled to a Hamamatsu R3941 PSPMT, a resistor chain circuit, preamplifiers, nuclear instrument modules, an analogue to digital converter and a PC for control and display. The intrinsic energy resolution of the system was 12.9% FWHM at 140 keV. The spatial resolution was measured using a line-slit mask and 99mTc point sources and was 3.1 mm FWHM. The intrinsic sensitivity of the system was approximately 162 counts/s kBq(-1). The DHC made it possible to image a larger FOV (75 x 75 mm2 at the surface of collimator) than a parallel-hole collimator (60 x 60 mm2). The system sensitivity obtained using the DHC gradually decreased with distance (3% at 1 cm, 6% at 2 cm and 9% at 3 cm). The results demonstrate that the system developed in this study could be utilized clinically to image malignant breast tumours. A DHC can be employed to expand the FOV of the system confined by the size of PSPMT with a modest compromise in the performance of the system.

High performance overdrive using improved motion adaptive codec in LCD

To improve overdrive performance in LCD, we present an improved motion adaptive codec (IMAC). The IMAC contains two approaches to improve the motion adaptive codec overdrive (MAC-OD). The first is an advanced hybrid image codec (AHIC) for the efficient reduction of the image data stored in frame memory. The second is an advanced motion adaptive selector to reduce the overdrive error. The simulation results show that the IMAC at 6.04:1 compression ratio significantly improves the overdrive performance by 2.268 dB in PSNR and achieves better visual quality compared with the conventional MAC-OD at 4:1 compression ratio. The IMAC is implemented with the Verilog HDL and fully synthesizable. It can be applied to shorten liquid crystal response time and minimize motion blur of LCD in TV and desktop applications.

A hybrid image coding in overdriving for motion blur reduction in LCD

Overdriving technique enlarges the desired change of the pixel value, the error in general compression methods is enlarged at the same time. Therefore, we propose a novel Adaptive Quantization Coding (AQC) to reduce the error in compression for overdriving technique reducing motion blur. Considering hardware implementation, we develop a hybrid image coding which uses color transform first, and then uses AQC to compress luminance data as well as Block Truncation Coding (BTC) to compress chrominance data. The simulation results shown that the average PSNR was improved 5.676dB as compared with the result of BTC, and the average SD of error was reduced 50.2% than that in the BTC. The proposed algorithm is implemented with the verilog HDL and synthesized with the synopsys design compiler using 0.13µm Samsung Library.

The efficient bus arbitration scheme in SoC environment

This paper presents the dynamic bus arbiter architecture for a system on chip design. The conventional bus-distribution algorithms, such as the static fixed priority and the round robin, show several defects that are bus starvation, and low system performance because of bus distribution latency in a bus cycle time. The proposed dynamic bus architecture is based on a probability bus distribution algorithm and uses an adaptive ticket value method to solve the impartiality and starvation problems. The simulation results show that the proposed algorithm reduces the buffer size of a master by 11% and decreases the bus latency of a master by 50%.

Two-Dimensional ESPRIT-Like Shift-Invariant TOA Estimation Algorithm Using Multi-Band Chirp Signals Robust to Carrier Frequency Offset

In this paper, a two-dimensional (2-D) ESPRIT-like shift-invariant time-of-arrival (TOA) estimation (ELSITE) algorithm for multi-band chirp signals in the presence of a carrier frequency offset (CFO) is presented. For the shift invariant TOA estimation, the received signals must be transformed into a sinusoidal form. When the received signals are perturbed by a CFO, the frequency of the transformed sinusoids is also shifted such that the TOA estimation results are biased. The TOA-induced phase shift of the multi-band chirp signals is determined according to the parameters of the signal, while the CFO-induced phase shift is only proportional to the elapsed time. Based on this property, the proposed ELSITE algorithm achieves robust TOA estimation against CFO from the signal subspace of the stacked matrix. The root mean square error of the proposed algorithm was analyzed and verified in both an AWGN channel and a multipath channel with CFO via Monte-Carlo simulations.

A Memory and Performance Optimized Architecture of Deblocking Filter in H.264/AVC

In this paper, we propose memory and performance optimized architecture to accelerate the operation speed of adaptive deblocking filter for H.264/JVT/AVC video coding. The proposed deblocking filter executes loading/storing and filtering operations with only 232 cycles for 1 macroblock. Only 2 times 4 times 4 internal buffers and 32 times 16 internal SRAM are adopted for the buffering operation of deblocking filter with I/O bandwidth of 32 bit. The proposed architecture can process the filtering operation for 1 macroblock with less filtering cycles and lower memory sizes than some conventional approaches of realizing deblocking filter. The efficient hardware architecture is implemented with novel data arrangement, hybrid filter scheduling and minimum number of buffer. The proposed architecture is suitable for low cost and real-time applications, and the real-time decoding with 1080HD (1920 times 1088 @ 30fps) can be easily achieved when working frequency is 85.2MHz.

A new Double Two-Way Ranging algorithm for ranging system

For wireless positioning system, a study on two-way ranging algorithms has been progressed to improve the accuracy of position estimates. In this paper, we propose an asynchronous Double Two-Way Ranging (D-TWR) algorithm, executing an overlapped Two-Way Ranging (TWR) effectively. In this way, the D-TWR algorithm can reduce the number of the required packets in the ranging algorithm as compared with that of the Symmetric Double Sided Two-Way Ranging (SDS-TWR) algorithm. Moreover, D-TWR can achieve more robust Time-of-Arrival (TOA) estimation than SDS-TWR by reducing the TOA estimation errors caused by clock crystal drift between two nodes.

Packet Detection and Symbol Timing Synchronization Algorithm for Multi-Band OFDM UWB

In this letter, we propose a novel packet detection and symbol timing synchronization algorithm for MB-OFDM UWB system over multi-path channel. To find more reliable and exact symbol timing, we utilize the merits of the auto- and cross-correlation at the same time. The auto-correlator can gather the energy of the received signal which is distorted by multipath fading. And, the cross-correlator can estimate symbol timing to sample level precision. We define the detection and symbol timing metric as the moving sum of autocorrelation of the pre-computed cross-correlated signals over zero pad duration. Simulation results show that the proposed algorithm can detect the presence of a signal with less than -4 dB SNR and find DFT window with at most 0.1 dB SNR reduction upon the receipt of two symbols.

A Subspace-Based Two-Way Ranging System Using a Chirp Spread Spectrum Modem, Robust to Frequency Offset

Herein, we propose and implement a subspace-based two-way ranging system for high resolution indoor ranging that is robust to frequency offset. Due to the frequency offset between wireless nodes, issues about sampling frequency offset (SFO) and carrier frequency offset (CFO) arise in range estimation. Although the problem of SFO is resolved by adopting the symmetric double-sided two-way ranging (SDS-TWR) protocol, the CFO of the received signals impacts the time-of-arrival (TOA) estimation, obtained by conventional subspace-based algorithms such as ESPRIT and MUSIC. Nevertheless, the CFO issue has not been considered with subspace-based TOA estimation algorithms.Our proposed subspace-based algorithm, developed for the robust TOA estimation to CFO, is based on the chirp spread spectrum (CSS) signals. Our subspace-based ranging system is implemented in FPGA with CSS modem using a hardware/software co-design methodology. Simulations and experimental results show that the proposed method can achieve robust ranging between the CSS nodes in an indoor environment with frequency offset.