Kyo-Min Sohn

A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture

This paper presents a hybrid-type TCAM architecture which can utilize the benefits of both NOR and NAND-type TCAM cells: high speed and low power. A hidden bank selection scheme is proposed to activate limited amount of cells during the search operation avoiding additional timing penalty. Match fine repeaters and sub-match fine scheme are used for fast NAND search operation. A test chip with 144-kb TCAM capacity is implemented using 0.1-/spl mu/m 1.2-V CMOS process to verify the proposed schemes. It shows 2.2 ns of match evaluation time on a 144-bit data search with 0.7 fJ/bit/search energy efficiency.

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

A higher performance DRAM is required by the market due to the increasing of bandwidth of networks and the rise of high-capacity multimedia content. DDR4 SDRAM is the next-generation memory that meets these demands in computing and server systems. In comparison with current DDR3 memory, the major changes are supply voltage reduction to 1.2V, pseudo open drain I/O interface, and data rate increase from 1.6 to 3.2Gb/s. To achieve high performance at low supply voltage and reduce power consumption, this work introduces new functions and describes their implementation. Data bus inversion (DBI) is employed for high-speed transactions to reduce power consumption of I/O and SSN noise. Dual-error detection, which adopts cyclic redundancy check (CRC) for DQ, and command address (CA) parity is designed to guarantee reliable transmission. GDDR5 memory also has DBI and CRC functions [1], but in this work, these schemes are implemented in a way that reduces area overhead and timing penalty. Besides these error-check functions, an enhanced gain buffer and a PVT-tolerant fetch scheme improve basic receiving ability. To meet the output jitter requirements of DDR4 SDRAM, the type of delay line for DLL is selected at initial stage according to data rate.

A Low-power Star-topology Body Area Network Controller for Periodic Data Monitoring Around and Inside the Human Body

More than hundred sensor devices are required to monitor various body signals. The body area network (BAN) connecting the sensor devices with the controller needs low power consumption and real-time operations, which is difficult to implement by conventional controller chips. In this paper, a low power controller chip is designed and fabricated to manage the proposed network with low power consumption. It periodically monitors the data from maximum 255 sensor devices with less than 2-mW power consumption. The controller is implemented in 25 mm silicon area and its operation is successfully demonstrated on the test system board.

An autonomous SRAM with on-chip sensors in an 80nm double stacked cell technology

An active solution to overcome the uncertainty and fluctuation in nano technology SRAM is introduced. It automatically adapts SRAMs operation optimized for the process variation and operating environments by using on-chip timer, temperature sensor, substrate noise manager and leakage current monitor. A test SRAM chip fabricated with an 80nm SRAM process, shows that average power consumption is reduced by 9%, and the standard deviation decreases by 58%.

A 833 Mb/s 2.5 V 4 Mb double data rate SRAM

A double-data-rate (DDR) SRAM overcomes the limitation of a single-data-rate (SDR) SRAM. The main features are an auto-tracking bitline scheme to reduce core cycle time, a shortened main data line for current reduction, a noise immune circuit having high-speed transfer characteristics through a dual-rail reset dynamic circuit, a two bit pre-fetched operation, and strobe clocks synchronized with the output data to guarantee CPU data-validation time.

An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology

An active solution is proposed to overcome the uncertainty and fluctuation of the device parameters in nanotechnology SRAM. The proposed scheme is composed of sensing blocks, analysis blocks and control blocks. An on-chip timer, temperature sensor, substrate noise detector, and leakage current monitor are used to monitor internal status of chip during operation. From the sensed data, internal supply voltage, internal timing margin from decoding to sensing time, substrate noise from digital area, and low voltage level of wordline are controlled. A 512-kb test SRAM chip, fabricated with an 80-nm double stacked cell technology, shows that average power consumption is reduced by 9% and the standard deviation decreases by 58%.

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Demand for higher bandwidth DRAM continues to increase, especially in high-performance computing and graphics applications. However, conventional DRAM devices such as DDR4 DIMM and GDDR5 cannot satisfy these needs since they are bandwidth limited to less than 30GB/s. Also, if multiple GDDR DRAMs are used simultaneously for higher bandwidth, then high power consumption and routing congestion on PCBs become a big concern. In order to overcome these limitations, the high-bandwidth memory (HBM) DRAM was recently introduced[1]. HBM-DRAM uses TSV and interposer technologies enabling multiple chip stacks and wide I/Os between the processor and memory: providing high capacity, low power and high bandwidth. This paper proposes the 2nd generation HBM to double the bandwidth from 128GB/s to more than 256GB/s and support pseudo-channel mode and 8H stacks [2]. In the pseudo-channel mode, a legacy channel is divided into two pseudo channels and the two pseudo channels share the command-address pins. Thus, one HBM has 16 pseudo channels instead of 8 legacy channels. To support various stack configurations including 8H stacks, a new architecture is adopted for flexible density ranging from 16Gb to 64Gb maintaining the same bandwidth. Finally, the bandwidth increase requires an active thermal solution to manage hotspots that develop from highly concentrated power consumption; we propose an adaptive refresh considering temperature distribution (ART) scheme as a solution.

A TCAM-based Periodic Event Generator for Multi-Node Management in the Body Sensor Network

Low-power periodic event generation is essential for a node controller in the network system with centralized control and the timer interrupt generation for various devices in a CPU. The proposed TCAM-based periodic event generator manages the issuing events with the programmed value and the number of the events is equal to the number of the word line of the TCAM block. The NAND-type TCAM cell operates with as low as 0.6 V supply voltage and the low-energy match line precharge reduces the search line transition which causes most of the search energy dissipation. The implemented event generator consumes 184-nJ energy to schedule events of 255 nodes for 24-hours, which is less than 10% of energy consumption of conventional hardware timer blocks.

A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy

As multi-core processors become mainstream, the demand for high-density cache memories has increased. Conventional 6T-cell-based SRAMs do not provide enough density for this trend, although they do have the desirable feature of high-speed access. To overcome the density limitation, an SRAM using a double- stacked S3 (stacked single-crystal Si) SRAM cell was introduced for mobile applications. This work demonstrates a high-speed SRAM using double-stacked-cell. From the process point of view, our design uses fully proven technologies for mass production at the sacrifice of cell size.From a circuit-design perspective, three schemes are introduced. They are automatic cell bias (ACB) for managing the current of SRAM cell transistors by controlling cell bias, adaptive block redundancy (ABR) for dealing with various defects from the new cell technology, and wordline pulse-width regulation (WPR) for adjusting wordline pulse-width according to cycle time.

Processor-Based Built-in Self-Optimizer for 90nm Diode-Switch PRAM

A PRAM includes 8 b embedded RISC to generate the optimized internal timing and voltage parameters to control the variations of the cell resistances. The PRAM blocks with small margin window of cell resistances are detected, analyzed and controlled by processor-based built-in self-optimizer (BISO). A 4 Mb test PRAM is fabricated in a 90 nm 3-metal diode-switch PRAM cell technology. Measured margin increases by up to 221%.