Sungdae Choi

A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications

A 121 mm/sup 2/ graphics LSI is for portable 2D/3D graphics and MPEG4 applications. The LSI contains a RISC processor with MAC, a 3D rendering engine, 29Mb DRAM and is built in a 0.16/spl mu/m pure DRAM technology. Programmable clocking allows the LSI to operate in several power modes for various applications. In lower cost mode, power consumption is under 210mW, delivering 264M texture mapped pixels per second.

A 0.9V 2.6mW Body-Coupled Scalable PHY Transceiver for Body Sensor Applications

An energy-efficient scalable PHY transceiver for body-coupled communications is presented. The analog front-end exploits pulse detection and cross-delayed sampling techniques. The digital baseband has a hierarchical block gating architecture for energy-efficient packet processing. The 0.18mum CMOS PHY transceiver chip operates up to 10Mb/s while consuming 2.6mW from a 0.9V supply

A Low-power Star-topology Body Area Network Controller for Periodic Data Monitoring Around and Inside the Human Body

More than hundred sensor devices are required to monitor various body signals. The body area network (BAN) connecting the sensor devices with the controller needs low power consumption and real-time operations, which is difficult to implement by conventional controller chips. In this paper, a low power controller chip is designed and fabricated to manage the proposed network with low power consumption. It periodically monitors the data from maximum 255 sensor devices with less than 2-mW power consumption. The controller is implemented in 25 mm silicon area and its operation is successfully demonstrated on the test system board.

A Low Power 16-bit RISC with Lossless Compression Accelerator for Body Sensor Network System

A low power 16-bit RISC is proposed for body sensor network system. The proposed IPEEP scheme provides zero overhead for the wakeup operation. The lossless compression accelerator is embedded in the RISC to support the low energy data compression. The accelerator consists of 16times16-bit storage array which has vertical and horizontal access path. By using the accelerator the energy consumption of the lossless compression operation is reduced by 93.8%. The RISC is implemented by 1-poly 6-metal 0.18 um CMOS technology with 16 k gates. It operates at 4 MHz and consumes 24.2 uW at 0.6 V supply voltage.

A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals

A low-power three-dimensional (3-D) rendering engine with two texture units and 29-Mb embedded DRAM is designed and integrated into an LSI for mobile third-generation (3G) multimedia terminals. Bilinear MIPMAP texture-mapped 3-D graphics can be realized with the help of low-power pipeline structure, optimization of datapath, extensive clock gating, texture address alignment, and the distributed activation of embedded DRAM. The scalable performance reaches up to 100 Mpixels/s and 400 Mtexels/s at 50 MHz. The chip is implemented with 0.16-/spl mu/m pure DRAM process to reduce the fabrication cost of the embedded-DRAM chip. The logic with DRAM takes 46 mm/sup 2/ and consumes 140 mW at 33-MHz operation, respectively. The 3-D graphics images are successfully demonstrated by using the fabricated chip on the prototype PDA board.

A TCAM-based Periodic Event Generator for Multi-Node Management in the Body Sensor Network

Low-power periodic event generation is essential for a node controller in the network system with centralized control and the timer interrupt generation for various devices in a CPU. The proposed TCAM-based periodic event generator manages the issuing events with the programmed value and the number of the events is equal to the number of the word line of the TCAM block. The NAND-type TCAM cell operates with as low as 0.6 V supply voltage and the low-energy match line precharge reduces the search line transition which causes most of the search energy dissipation. The implemented event generator consumes 184-nJ energy to schedule events of 255 nodes for 24-hours, which is less than 10% of energy consumption of conventional hardware timer blocks.

A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications

A low-power graphics LSI is designed and implemented for mobile multimedia applications. The LSI contains a 32bit RISC processor with enhanced MAC, a 3D rendering engine, programmable power optimizer, and 29Mb embedded DRAM. Full 3D graphics pipeline featuring 264Mtexels/s texture-mapped 3D graphics as well as 2D MPEG-4 video decoding can be realized while consuming less than 210mW and 121mm2 chip area. The chip is implemented with 0.16μm pure DRAM process to reduce the fabrication cost. The real-time 3D graphics applications are successfully demonstrated by the fabricated chip on two PDA system boards.

A low power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3G multimedia terminals

A low-power 3D rendering engine with 2 texture units and 29Mb embedded DRAM is designed and integrated into an LSI for portable 3G multimedia terminals. Texture-mapped 3D graphics with perspective-correct address calculation and bilinear MIPMAP filtering can be realized while consuming the low power with the help of clock gating, precision-controlled look-up table dividers, texture address alignment and embedded DRAM. The performance is scalable and it reaches up to 100Mpixels/s and 400 Mtexles/s at 50MHz. The chip is implemented with 0.16/spl mu/m pure DRAM process to reduce the fabrication cost. The logic and DRAM consume 46mm/sup 2/ and 140mW at 33MHz operation. The 3D graphics images are successfully demonstrated by the fabricated chip on the PDA system board.

A Low Power Compression Processor for Body Sensor Network System

A low power 16-bit RISC is proposed for body sensor network system. The RISC is designed of basic 3 stage pipeline architecture which has 28 instruction sets. Some special instructions are proposed for efficient applications. The lossless compression accelerator is embedded in the RISC to support the low energy data compression. The accelerator consists of 16×16-bit storage array which has vertical and horizontal access path. By using the accelerator the energy consumption of the lossless compression operation is reduced by 95%. The RISC is implemented by 1-poly 6-metal 0.18um CMOS technology with 16k gates. It operates at 4MHz and consumes 24.2uW at 0.6V supply voltage.

An Ultra Low-Power Body Sensor Network Control Processor with Centralized Node Control

A body sensor network (BSN) system needs ultra-low power consumption to provide a user-friendly small form-factor. This paper presents the dual-mode system architecture to manage 254 nodes in the BSN with low-power consumption. Its instantaneous program execution with external program counter scheme prohibits unnecessary RISC operation and wakes up the RISC from its turn-off state just in 3-clock cycles, the same as reset sequence. The TCAM-based periodic event generator manages 254 periods of each network node with low energy consumption. The implemented test chip consumes 24.2muW average power for 254 nodes management and 4.2-MIPS performance