Hyun-Geun Byun

A 0.1-

A 256-Mb phase-change random access memory has been developed, featuring 66-MHz synchronous burst-read operation. Using a charge pump system, write performance was characterized at a low supply voltage of 1.8 V. Measured initial read access time and burst-read access time are 62 and 10 ns, respectively. The write throughput was 0.5 MB/s with internal times2 write and can be increased to ~2.67 MB/s with times16 write. Endurance and retention characteristics are measured to be 107 cycles and ten years at 99 degC

\mu{\hbox {m}}

A non-volatile 64 Mb phase-transition RAM is developed by fully integrating a chalcogenide alloy GST (Ge/sub 2/Sb/sub 2/Te/sub 5/) into 0.18 /spl mu/m CMOS technology. This alloy is programmed by resistive heating. To optimize SET/RESET distribution, a 512 kb sub-core architecture, featuring meshed ground line, is proposed. Random read access and write access for SET/RESET are 60 ns, 120 ns and 50 ns, respectively, at 3.0 and 30/spl deg/C.

1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

A 1.8 V 64 Mb phase-change RAM with improved write performance is fabricated in a 0.12 /spl mu/m CMOS technology. The improvement of RESET and SET distributions is based on cell current regulation and multiple step-down pulse generators. The read access time and SET-write time are 68 ns and 180 ns respectively.

A 0.18 /spl mu/m 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)

This paper presents a hybrid-type TCAM architecture which can utilize the benefits of both NOR and NAND-type TCAM cells: high speed and low power. A hidden bank selection scheme is proposed to activate limited amount of cells during the search operation avoiding additional timing penalty. Match fine repeaters and sub-match fine scheme are used for fast NAND search operation. A test chip with 144-kb TCAM capacity is implemented using 0.1-/spl mu/m 1.2-V CMOS process to verify the proposed schemes. It shows 2.2 ns of match evaluation time on a 144-bit data search with 0.7 fJ/bit/search energy efficiency.

Enhanced write performance of a 64 Mb phase-change random access memory

An active solution to overcome the uncertainty and fluctuation in nano technology SRAM is introduced. It automatically adapts SRAMs operation optimized for the process variation and operating environments by using on-chip timer, temperature sensor, substrate noise manager and leakage current monitor. A test SRAM chip fabricated with an 80nm SRAM process, shows that average power consumption is reduced by 9%, and the standard deviation decreases by 58%.

A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture

A new programmable and automatically adjustable off-chip driver (OCD) and on-die terminator (ODT) for DDR3-SRAM interface are proposed, to widen the valid data widow. The proposed OCD fills the role of the ODT, and the OCD and the ODT play a role in the ESD protection circuit. This application of 72 Mb DDR3-SRAM provides a 1.5 GHz data rate, and the valid data window of the DDR input signal is 540 ps. The proposed programmable impedance controller (PIC) maintains constant resistance of the ODT within a 3% variation, and supports DDR3-SRAM mode. A new scheme of updating impedance control codes to maintain uniform impedance and a stable power-up sequence for the ODT are also suggested.

An autonomous SRAM with on-chip sensors in an 80nm double stacked cell technology

A 256Mb PRAM featuring synchronous burst read operation is developed. Using a charge-pump system, write performance is characterized at 1.8V supply. Measured initial read access time and burst-read access time are 62ns and 10ns, respectively. The maximum write throughput is 3.3MB/S

Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface

This paper presents a digitally controlled oscillator (DCO) for high speed ADPLLs. The proposed DCO circuit has control codes of thermometer type, which can reduce jitters. Performance of the DCO is verified through a novel ADPLL. The ADPLL chip with the DCO was fabricated using a 0.18mum CMOS technology. The ADPLL has operation range between 520MHz and 1.5GHz and has 76ps peak-to-peak jitter at 668MHz

A 0.1/spl mu/m 1.8V 256Mb 66MHz Synchronous Burst PRAM

This paper describes an adaptive cell bias scheme that is proposed to achieve high performance and stability for a low power, high speed, and high density SRAM core with less process variation. The proposed scheme is featured with constrained-successive cell bias optimization method that determines the optimal cell bias condition sequentially to meet both the speed and stability target of a given SRAM core. The architecture with adaptive cell bias scheme is applied to a 144Mb double stacked S3 SRAM and leads to 49% reduction in SRAM core performance parameter variations with 8% area overhead. The power reduction is 21%

A Digitally Controlled Oscillator for Low Jitter All Digital Phase Locked Loops

An active solution is proposed to overcome the uncertainty and fluctuation of the device parameters in nanotechnology SRAM. The proposed scheme is composed of sensing blocks, analysis blocks and control blocks. An on-chip timer, temperature sensor, substrate noise detector, and leakage current monitor are used to monitor internal status of chip during operation. From the sensed data, internal supply voltage, internal timing margin from decoding to sensing time, substrate noise from digital area, and low voltage level of wordline are controlled. A 512-kb test SRAM chip, fabricated with an 80-nm double stacked cell technology, shows that average power consumption is reduced by 9% and the standard deviation decreases by 58%.