Kyoung-Ho Jung

A Full FinFET DRAM Core Integration Technology Using a Simple Selective Fin Formation Technique

A full FinFET DRAM core which consists of McFETs for both the sense amplifiers and the sub-word drivers, as well as FinFETs for the memory cell array has been developed. It will efficiently shrink chip size and improve chip performance, and therefore, meet requirements for the future DRAMs with 55nm or smaller design rule. Newly developed schemes which are a selective STT SiN liner removal process, a selective TiN gate stack and narrow active pitch patterning have been successfully integrated

Effective work function engineering for a TiN/XO(X = La, Zr, Al)/SiO2 stack structures

In this study, we demonstrated that work function engineering is possible over a wide range (+200 mV to −430 mV) in a TiN/XO (X = La, Zr, or Al)/SiO2 stack structures. From ab initio simulations, we selected the optimal material for the work function engineering. The work function engineering mechanism was described by metal diffusion into the TiN film and silicate formation in the TiN/SiO2 interface. The metal doping and the silicate formation were confirmed by transmission electron microscopy and energy dispersive spectroscopy line profiling, respectively. In addition, the amount of doped metal in the TiN film depended on the thickness of the insertion layer XO. From the work function engineering technique, which can control a variety of threshold voltages (Vth), an improvement in transistors with different Vth values in the TiN/XO/SiO2 stack structures is expected.

Direct evidence of flat band voltage shift for TiN/LaO or ZrO/SiO 2 stack structure via work function depth profiling

We demonstrated that a flat band voltage (VFB) shift could be controlled in TiN/(LaO or ZrO)/SiO2 stack structures. The VFB shift described in term of metal diffusion into the TiN film and silicate formation in the inserted (LaO or ZrO)/SiO2 interface layer. The metal doping and silicate formation confirmed by using transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS) line profiling, respectively. The direct work function measurement technique allowed us to make direct estimate of a variety of flat band voltages (VFB). As a function of composition ratio of La or Zr to Ti in the region of a TiN/(LaO or ZrO)/SiO2/Si stack, direct work function modulation driven by La and Zr doping was confirmed with the work functions obtained from the cutoff value of secondary electron emission by auger electron spectroscopy (AES). We also suggested an analytical method to determine the interface dipole via work function depth profiling.

A Novel Multi-Fin DRAM Periphery Transistor Technology using a Spacer Transfer through Gate Polysilicon Technique

Abstract A new technique which integrates the metal gate multi-FinFETs and the conventional polysilicon gate planar FETs is proposed. It solves the problems of conventional scheme, such as complication of process integration due to coexistence of TiN gate FinFETs and polysilicon gate planar FETs, fin width consumption by multi gate oxidation, large fin-pitch limited by lithography and STI gap-filling. A newly proposed technique forms multi-fin structure by spacer transfer process through gate polysilicon electrode of planar FETs. Drain current gain due to increase of effective channel width is estimated and basic electrical characteristics of multi-FinFET are evaluated.