Keunnam Kim

Recessed Channel Fin Field-Effect Transistor Cell Technology for Future-Generation Dynamic Random Access Memories

A new bulk fin field-effect transistor (bulk FinFET) with a recessed channel structure is proposed as a future dynamic random access memory (DRAM) cell transistor following the recess-channel-array transistor (RCAT). An enlarged effective channel length improves the relationship between off-state channel leakage (Ioff) and gate-induced drain leakage (GIDL) current, which correspond to the static and dynamic retention characteristics of a DRAM chip. The high current drivability of FinFET is maintained even with a recessed channel. A recessed-channel FinFET (RC-FinFET) shows excellent DC characteristics (subthreshold swing, drain-induced barrier lowering and body-bias effect) and longer retention time than a conventional local-damascene FinFET (LD-FinFET).

Study on the Retention Time of Body Tied FINFET DRAM with Channel Directional Wafer

A negative word line (NWL) bias scheme is adapted to the body tied finFET DRAM. But, increased gate induced drain leakage (GIDL) degrade data retention time. The retention time of lang100rang channel directional wafer (CW) was compared to that of lang110rang CW. Using lang100rang CW to the finFET DRAM, the reduced GIDL current improve the data retention time

The application of BT-FinFET technology for sub 60nm DRAM integration

In this paper, the application of body tied FinFET is presented for a technology breakthrough beyond sub 60nm. DRAM on bulk Si substrate has been successfully integrated and the characteristics were compared to recess channel and planar cell array transistor DRAM. We present a comparison of three different device structures and show damascene BT-FinFET using NWL (negative word line) scheme with low channel for a highly manufacturable DRAM for sub 60nm technology node.

Optimization of Layout and Doping Profile Design for BT(Body Tied)-FinFET DRAM

In this paper, a device design guideline of sub 60nm BT-FinFET (Body Tied Fin FET) DRAM cell transistor is proposed. The VT controllability and variation were compared for 3 different implant concepts (blanket, local channel, and asymmetric S/D) and 2 different fin active designs (uneven and straight active type). Those were systemically analyzed for sub 60nm BT-FinFET device. And finally, the optimal structure for mass production is discussed. Introduction Body tied FinFET cell DRAM has been intensively investigated [1-2] to introduce this technology to mass production early as possible. And NWL (Negative Word Line) and damascene technology were successfully applied to 512M FinFET DRAM. Based on the damascene FinFET DRAM process, LCI (Local Channel Implantation) on FinFET was shown excellent data retention time owing to reducing unnecessary boron dopant at the n+ storage node and nregion. And <100> channel direction scheme was also introduced to increase the saturation current and speed by maximize the electron mobility. However, the boron dopant at the LCI region diffuses to the storage node resulting in unwanted junction leakage increment. And the saucer type uneven active was not effective for using <100> CW (Channel direction Wafer) [4] because it has a concaved channel direction. Therefore, we have investigated a design of active fin and channel VT control methods. In this paper, we present several critical points of device design consideration of body tied FinFET DRAM such as the active fin design, NWL, refresh characteristics and FinFET VT control. Experimental The highly manufacturable 512M damascene BT-FinFET DRAM was integrated on p-type bulk Si (100) wafer by using 80nm body tied finFET process technology [2] (Fig. 1-(a)). And LCI (Local Channel Implantation), Blanket and ASD (Asymmetric Source Drain) implantation methods (Fig. 1-(b)) were split on d-FinFET (damascene FinFET) DRAM having 2 different active designs (Fig. 2). As can be seen clearly, straight active designed FinFET shows uniform fin width of 60nm from storage node edge “A” to bit line node edge “B” while uneven active FinFET shows thicker fin width at “B” side. The refresh characteristics of FinFET DRAM were evaluated for negative word line potential versus FinFET threshold voltage and 3 different implantation schemes. Results and Discussion The dynamic and static refresh characteristics of 512M d-FinFET were evaluated to find a relationship between NWL and VTC (Threshold voltage of Cell Tr.) of FinFET (Fig. 3). It is shown that approximately -0.6 ~ -0.8V range of NWL potential was required to minimize both dynamic and static fail bit for a FinFET cell Tr. having low (~0.1V) cell threshold voltage. And the range can be increased when higher VTC was used because the dynamic refresh fail was suppressed at lower NWL where the increasing of static fail bit is still negligible. Therefore, the minimum VTC was found to accomplish the operational refresh margin. However, the threshold voltage adjustment is more difficult for thinner body FinFET due to segregation of boron at the 3D fin surface. And it is ultimately difficult for DRAM because storage node junction leakage current is very sensitive to increasing of boron dopant. ASD (Asymmetric Source Drain) implantation scheme was then applied to minimize the boron effects on storage node junction leakage. Fig. 4 shows ASD device having the lowest storage node junction leakage current over the blanket implant and LCI scheme. However, the bit line node leakage current difference was minimized which has negligible effect on refresh characteristics. In Fig. 6, the threshold voltage controllability of uneven and straight type active design. ASD implantation was used and found that the VT control of uneven active FinFET can be easier than that of straight active. It was important result because the uneven active has been conventionally used to achieve enough alignment margins after gate pattering for bit line contact. Fig. 7 shows Id-Vg characteristics of ASD implanted FinFET DRAM cell. It indicates one cell transistor can have two different VT for operation conditions and VT of write “1” condition is about 350mV lower than read “1” condition. It is a great advantage that the data “1” can be easily written for ASD FinFET. However, the threshold voltage distributions of both active designs indicate a demerit of uneven active FinFET cell transistor (Fig. 8). Also VT distribution of 80nm RCAT (Recess Channel Array Transistor) [3], FinFET with ASD and thin body transistor with TiN gate were compared. The uneven active FinFET with ASD shows large VT distribution while recess channel array transistor and straight active FinFET with ASD show negligible distribution. It is quit clear that RCAT or straight active design is acceptable for mass production. However, FinFET cell array transistor has several advantages over RCAT besides VT distribution for being used sub 60nm regime [1]. Therefore, based on these result, the optimal design scheme of FinFET DRAM is straight active combined with ASD or workfunction optimized gate since NWL (Negative Word Line) scheme was found to be an optimal solution for body tied FinFET DRAM. Finally, the refresh characteristics of 3 different VT adjustment implant scheme were evaluated (Fig. 10) and found the ASD implanted 512M FinFET DRAM shows superior characteristics over the others. Fig. 11 shows the expected VT of sub 40nm FinFET cell DRAM by using 4.7 ~ 5.1eV gate material and minimum required VT can be lowered for FinFET with NWL and high workfunction gate material while maintaining minimum Ion/Ioff ratio requirement of 10. Conclusion In this paper, we systemically analyze 80nm body tied FinFET cell array transistor DRAM for the fin active design and device design schemes. Based on consideration of VT controllability, distribution and refresh margin, straight active design with ASD (Asymmetric Source Drain) scheme was found to be the best structure for production of BT-FinFET DRAM. References [1] C. H. Lee, et al., VLSI 2004, 13.3, p130. [2] C. Lee, et al., IEDM 2004, 3.2, p61. [3] H. S. Kim, et al., IEDM 2003, 17.2, p411. [4] T. Komoda, et al., IEDM2004, 9.3, p217. Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials, Kobe, 2005, -184H-1-2 pp.184-185

Three Series-Connected Transistor Model for a Recess-Channel-Array Transistor and Improvement of Electrical Characteristics by a Bottom Fin Structure

A three series-connected transistor model is introduced to understand the electrical characteristics of conventional recess-channel-array transistors (RCATs) and modified RCATs. An RCAT is considered to be a serial connection of three transistors consisting of one bottom transistor and two vertical transistors. The electrical characteristics of a cell transistor are explained by a balance of those transistors. A newly modified fin-RCAT which has a fin structure at the bottom of a silicon recess is proposed to improve cell transistor characteristics. This design improves cell current by 70% while maintaining retention characteristics.

A Novel Multifin Dynamic Random Access Memory Periphery Transistor Technology Using a Spacer Patterning through Gate Polycrystalline Silicon Technique

A new technique that integrates the metal gate multifin field effect transistor (multi-FinFET) and the conventional polycrystalline silicon (poly-Si) gate planar FET is proposed. It solves the problems of the previous scheme, such as the complicated process integration due to the coexistence of TiN gate FinFETs and poly-Si gate planar FETs, the fin width consumption by multiple gate oxidation, the large fin pitch limited by the resolution of lithography, and the gap-filling ability of shallow trench isolation (STI). The newly proposed technique forms multifin structures by spacer patterning through the gate poly-Si electrode for planar FETs. The drain current gain due to an increase in effective channel width is estimated, and the basic electrical characteristics of a multi-FinFET are evaluated.

Investigation of Body Bias Dependence of Gate-Induced Drain Leakage Current for Body-Tied Fin Field Effect Transistor

The body bias dependence of gate-induced drain leakage (GIDL) current for a fin field effect transistor fabricated on a bulk Si wafer (bulk FinFET) is investigated. The local damascene (LD) bulk FinFET is measured under various bias conditions and the effect of the body-bias-induced lateral electric field on GIDL current is evaluated. A lateral electric field shield effect under fin depleted condition is proposed and it is validated by the three-terminal band-to-band tunneling current model. The GIDL current of the bulk FinFET can be reduced by reducing the body bias, and an improvement in retention characteristics is expected.