Hyunju Sung

A Full FinFET DRAM Core Integration Technology Using a Simple Selective Fin Formation Technique

A full FinFET DRAM core which consists of McFETs for both the sense amplifiers and the sub-word drivers, as well as FinFETs for the memory cell array has been developed. It will efficiently shrink chip size and improve chip performance, and therefore, meet requirements for the future DRAMs with 55nm or smaller design rule. Newly developed schemes which are a selective STT SiN liner removal process, a selective TiN gate stack and narrow active pitch patterning have been successfully integrated

Recessed Channel Fin Field-Effect Transistor Cell Technology for Future-Generation Dynamic Random Access Memories

A new bulk fin field-effect transistor (bulk FinFET) with a recessed channel structure is proposed as a future dynamic random access memory (DRAM) cell transistor following the recess-channel-array transistor (RCAT). An enlarged effective channel length improves the relationship between off-state channel leakage (Ioff) and gate-induced drain leakage (GIDL) current, which correspond to the static and dynamic retention characteristics of a DRAM chip. The high current drivability of FinFET is maintained even with a recessed channel. A recessed-channel FinFET (RC-FinFET) shows excellent DC characteristics (subthreshold swing, drain-induced barrier lowering and body-bias effect) and longer retention time than a conventional local-damascene FinFET (LD-FinFET).

Interlayer design verification methodology using contour image

Memory industry has been pursuing endless shrinking technology which increases fabrication complexity. It poses problems between adjacent layers as well as within a single layer. To verify the interlayer design, we have developed the interlayer design verification methodology using contour image. Our methodology makes it possible to verify interlayer design visually by extracting the contour image from the real patterns. And we can verify interlayer design even during the fabrication process and conduct a non-destructive inspection. Also this methodology provides a statistical analysis of massive measured data. Through this methodology, we can calculate the margin of current interlayer design and suggest the requirement of design.

A novel methodology for building robust design rules by using design based metrology (DBM)

This paper addresses a methodology for building robust design rules by using design based metrology (DBM). Conventional method for building design rules has been using a simulation tool and a simple pattern spider mask. At the early stage of the device, the estimation of simulation tool is poor. And the evaluation of the simple pattern spider mask is rather subjective because it depends on the experiential judgment of an engineer. In this work, we designed a huge number of pattern situations including various 1D and 2D design structures. In order to overcome the difficulties of inspecting many types of patterns, we introduced Design Based Metrology (DBM) of Nano Geometry Research, Inc. And those mass patterns could be inspected at a fast speed with DBM. We also carried out quantitative analysis on PWQ silicon data to estimate process variability. Our methodology demonstrates high speed and accuracy for building design rules. All of test patterns were inspected within a few hours. Mass silicon data were handled with not personal decision but statistical processing. From the results, robust design rules are successfully verified and extracted. Finally we found out that our methodology is appropriate for building robust design rules.

Three Series-Connected Transistor Model for a Recess-Channel-Array Transistor and Improvement of Electrical Characteristics by a Bottom Fin Structure

A three series-connected transistor model is introduced to understand the electrical characteristics of conventional recess-channel-array transistors (RCATs) and modified RCATs. An RCAT is considered to be a serial connection of three transistors consisting of one bottom transistor and two vertical transistors. The electrical characteristics of a cell transistor are explained by a balance of those transistors. A newly modified fin-RCAT which has a fin structure at the bottom of a silicon recess is proposed to improve cell transistor characteristics. This design improves cell current by 70% while maintaining retention characteristics.

A Novel Multifin Dynamic Random Access Memory Periphery Transistor Technology Using a Spacer Patterning through Gate Polycrystalline Silicon Technique

A new technique that integrates the metal gate multifin field effect transistor (multi-FinFET) and the conventional polycrystalline silicon (poly-Si) gate planar FET is proposed. It solves the problems of the previous scheme, such as the complicated process integration due to the coexistence of TiN gate FinFETs and poly-Si gate planar FETs, the fin width consumption by multiple gate oxidation, the large fin pitch limited by the resolution of lithography, and the gap-filling ability of shallow trench isolation (STI). The newly proposed technique forms multifin structures by spacer patterning through the gate poly-Si electrode for planar FETs. The drain current gain due to an increase in effective channel width is estimated, and the basic electrical characteristics of a multi-FinFET are evaluated.

A Novel Multi-Fin DRAM Periphery Transistor Technology using a Spacer Transfer through Gate Polysilicon Technique

Abstract A new technique which integrates the metal gate multi-FinFETs and the conventional polysilicon gate planar FETs is proposed. It solves the problems of conventional scheme, such as complication of process integration due to coexistence of TiN gate FinFETs and polysilicon gate planar FETs, fin width consumption by multi gate oxidation, large fin-pitch limited by lithography and STI gap-filling. A newly proposed technique forms multi-fin structure by spacer transfer process through gate polysilicon electrode of planar FETs. Drain current gain due to increase of effective channel width is estimated and basic electrical characteristics of multi-FinFET are evaluated.