Kyoungwon Min

HOG feature extractor circuit for real-time human and vehicle detection

Smart vehicle technologies such as ADAS are growing concern about. Especially, pedestrian and vehicle recognition system based on machine vision is a big issue. In this paper, we propose the hardwired HOG feature extractor circuit for real-time human and vehicle detection, and describe the hardware implementation results. Our HOG feature extractor supports weighted gradient value, 2D histogram interpolation and block normalization. We have used the simplified methods of the square root and division operation for the hardware implementation. Our HOG feature extractor circuit was verified on FPGA environment and can be processed 33 frames per seconds for 640×480 VGA images in real-time.

Real-time pedestrian detection based on A hierarchical two-stage Support Vector Machine

This Paper presents an SVM (Support Vector Machine) based real-time pedestrian detection scheme for next-generation automotive vision applications. To meet the requirement of real-time detection with high accuracy, we designed the proposed system consisting of 2-stage hierarchical SVMs. In the proposed system, most of the input data are classified by the 1st stage linear SVM and only the inputs between positive and negative hyper-plane of the linear SVM are transferred to the 2nd stage non-linear SVM. This hierarchical 2-stage classifier can be suited for various systems via controlling the amount of data processed by the 2nd stage classifier, which trades off the detection accuracy and the required system resources. To make the proposed 2nd stage non-linear SVM further appropriate for various systems, a hyper-plane approximation technique by sample pruning has been adopted. By reducing the number of required SVs (Support Vectors) using this technique and controlling the amount of data processed via the 2nd stage classifier, high precision non-linear SVM can be employed in the proposed real-time pedestrian detection system. Simulations using HOG (Histogram of Oriented Gradient) features and Daimler pedestrian dataset show the proposed system provides highly accurate classification results under the real-time constraint of application.

Efficient and real-time stereo matching hardware architecture for high-resolution image

In this paper, we propose an efficient and real-time stereo matching hardware architecture for a high resolution image. Disparity estimation algorithm must be operated at a real-time to be of practical use for applications such as an autonomous driving. However, they generally require large computational efforts and high memory capacities in the embedded processor-based systems. To solve this problem, we studied the real-time stereo matching hardware architecture and implemented in hardware system. Our architecture was implemented using Verilog HDL. Our circuit uses 95% LUT, 92% FF and 80% BRAM of Zynq XC7Z020 FPGA. Also, our hardware circuit can generate the depth data for the high-resolution images which receive from cameras without delays in the real time.

Real-time dense stereo matching architecture for high-resolution image

In this paper we propose a real-time dense stereo matching architecture for a high-resolution image. Stereo matching shows the best performance to detect objects and to estimate distance detection. So, many algorithms have been developed, such as local matching and global matching. Disparity estimation algorithm should run at real-time to be of practical use for applications such as autonomous driving. However, they generally require large computational efforts and high memory capacities. To solve this problem, we adopt the ELAS algorithm and implemented in hardware for the real-time operation. Our architecture was implemented using Verilog HDL. Our circuit is composed of 770,305 logic gates and 3,638,016 bits internal memory. Also, our hardware architecture can extract the disparity map for the images which receive from cameras without delay in real time.

Detecting Fingertip Robust Scale-Invariant and Rotation Invariant with Stereo Camera

Recently, Many IT products applying the gesture recognition are developed. To recognize the hand gesture, We need technology that detect fingertip. When we detect the hand using the depth of Stereo Camera in the previous method, It couldn`t separate the hand and the wrist. In this paper, we can detect separately hand, wrist and fingertip using the depth of Stereo Camera. Hand was detected by AND operation between skin color filter and disparity-map from Stereo Camera. To detect the fingertip on the detected hand, we use accumulation value of in Sub-window. Fingertips were detected by each of X, Y axis accumulation value in Sub-window on the hand region. Our method has advantages that it is scale-invariant and rotation invariant. So we can process Natural User Interface. As the experiment result indicated, our proposed detection performance is the average 96.58%.

Efficient hardware architecture for real-time Semi-Global Matching

In this paper we propose an efficient hardware architecture for real-time SGM (Semi-Global Matching). SGM has a robust characteristic than previous local stereo matching algorithms. But SGM requires high computational loads and extremely high memory bandwidth to store intermediate results. To overcome these problems, we have maximized data parallelism by adopting systolic array and pipelining. Also we have maximized internal memory recycling efficiency to minimize memory bandwidth. With this method, our architecture not only processes 32 frame of VGA disparity images per second at 100MHz operating frequency but also do not requires external memory to store intermediate data. Our architecture was implemented using Verilog HDL. Our circuit is composed of 529,200 logic gates and 2,030,784 bits internal memory. Disparity map of SGM circuit has been verified using the Middlebury test images and the average error rate is 6.22%.

Design of unified support vector machine circuit for pedestrians and cars detection

This paper describes the design of unified support vector machine circuit for pedestrians and cars detection. By unifying the algorithms and architectures of linear and nonlinear SVM classifications, the proposed circuit can support both linear and non-linear classifications very efficiently in terms of circuit size and performance. The circuit size is minimized by sharing most of the resources required in the computation for both classification types. Parallel architecture with pipeline is adopted to accelerate the processing speed to handle a large amount of operations for real-time processing. 48×96 and 64×64 sliding windows with 6 window strides are used to detect pedestrians and cars, respectively. The synthesized circuit using 65nm standard cell library consists of 848,349 gates and its maximum operating frequency is 435MHz. The circuit can process 91.9 640×480 image frames per second assuming three cameras equipped on front, right and left side positions of the vehicle.