Yong Ho Song

A progressive approach to handling message-dependent deadlock in parallel computer systems

Handling deadlocks is essential for providing reliable communication paths between processing nodes in parallel computer systems. The existence of multiple message types and associated inter-message dependencies may cause message-dependent deadlocks in networks that are designed to be free of routing deadlock. Most methods currently used for dealing with message-dependent deadlocks require more system resources than are necessary and/or do not use system resources efficiently. This may have an adverse effect on system performance if resources are scarce. In this paper, we characterize the frequency of message-dependent deadlocks in multiprocessor/multicomputer systems. We also propose a handling technique for message-dependent deadlocks based on progressive deadlock recovery and evaluate its performance with other approaches. Results show that message-dependent deadlocks occur very infrequently under typical circumstances thus, rendering approaches based on avoiding them overly restrictive in the common case. The proposed technique relaxes restrictions considerably, allowing the routing of packets and the handling of message-dependent deadlocks to be much more efficient-particularly when network resources are scarce.

FRA: a flash-aware redundancy array of flash storage devices

Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as storage media in the embedded and computer system environments. In the case of reliability, however, there are many shortcomings in flash memory: potentially high I/O latency due to erase-before-write and poor durability due to limited erase cycles. To overcome these problems, a RAID technique borrowed from storage technology based on hard disks is employed. In the RAID technology, multi-bit burst failures in the page, block or device are easily detected and corrected so that the reliability can be significantly enhanced. However the existing RAID-5 scheme for the flash-based storage has delayed response time for parity updating. To overcome this problem, we propose a novel approach using a RAID technique in flash storage, called Flash-aware Redundancy Array. In this approach, parity updates are postponed so that they are not included in the critical path of read and write operations. Instead, they are scheduled for when the device becomes idle. For example, the proposed scheme shows a 19% improvement in the average write response time, compared to other approaches.

A process-aware hot/cold identification scheme for flash memory storage systems

NAND flash memory has attractive features compared to hard disk drives such as small size, no mechanical noise and shock resistance. But it also has some drawbacks such as no support for in-place updates and limited program/erase cycles, which trigger the development of sophisticated buffer management algorithms in order to reduce write and/or erase operations to flash memory. The significant gap in update frequency between hot and cold data motivates us to separate hot and cold data on different flash blocks to avoid unnecessary program/erase cycles. Many buffer management algorithms determine a request to be hot or cold based on its requested data size. However, the data size could become a wrong indicator of update frequency in many applications. In this paper, we propose a new hot/cold identification scheme in order to increase identification accuracy and, thus, to enhance storage performance and durability by reducing program/erase cycles. The proposed technique uses the process identification used in many operating systems as a hot/cold indicator. The experimental results show that the proposed scheme contributes to high performance and durability as compared to previously proposed identification schemes.

Hierarchical architecture of flash-based storage systems for high performance and durability

The use of NAND flash memory for building permanent storage has been increasing in many embedded systems due to properties such as non-volatility and low enery consumption. The persistent requirements for high storage capacity have given rise to the increase of bit density per cell as in multi-level cells but this has come at the expense of performance and has resulted in degradation of durability. In this paper, we introduce a complementary approach to boost the performance and durability of MLC-based storage systems by employing a non-volatile buffer that temporarily holds the data heading to MLCs. We also propose algorithms to efficiently eliminate unnecessary write and erase operations in MLCs by performing a pre-merge in the buffer. Our experiments show that the proposed approach can increase performance by up to 4 times and durability by 4 times by adding only a small hardware cost.

Distributed resolution of network congestion and potential deadlock using reservation-based scheduling

Efficient and reliable communication is essential for achieving high performance in a networked computing environment. Finite network resources bring about unavoidable competition among in-flight network packets, resulting in network congestion and, possibly, deadlock. Many techniques have been proposed to improve network performance by efficiently handling network congestion and potential deadlock. However, none of them provide an efficient way of accelerating the movement of network packets in congestion toward their destinations. In this paper, we propose a new mechanism for detecting and resolving network congestion and potential deadlocks. The proposed mechanism is based on efficiently tracking paths of congestion and increasing the scheduling priority of packets along those paths. This acts to throttle other packets trying to enter those congested regions - in effect, locking out packets from congested regions until congestion has had the opportunity to disperse. Simulation results show that the proposed technique effectively disperses network congestion and is also applicable in helping to resolve potential deadlock.

Write-aware buffer management policy for performance and durability enhancement in NAND flash memory

The popularity of NAND flash memory has been growing rapidly in recent years, but the SSD (Solid-State Disk) has shown limited success in its battle against the hard disk. Besides the high price, SSD suffers performance degradation under random write requests, due to the intrinsic weak points of NAND flash: erase-before-write, asymmetric read/write access time, and limited program/erase cycles. In order to overcome these drawbacks, many buffer replacement algorithms have been proposed. However, considering the cost of write operations, it would be beneficial to have dirty pages updated before being flushed to flash memory. In this paper, we propose a new buffer management scheme to retain write-intensive pages in the buffer, and we confirm its effectiveness by applying it to one of the existing buffer management schemes. The simulation results indicate that the proposed scheme reduces up to 30% of the write count, and, therefore, extends the lifetime of NAND flash memories.

Architecture exploration of flash memory storage controller through a cycle accurate profiling

Recently, NAND flash memory has been widely adopted as a storage medium in various devices such as mobile phones, MP3 players, and digital cameras. In particular, Solid State Drives (SSDs), which are composed of multiple NAND flash memories, have gradually replaced hard disk drives (HDD). However, SSDs have an inherent weakness stemming from NAND flash memory and its complex architecture. This phenomenon makes it difficult to analyze and optimize the performance of SSD controllers. To overcome this weakness, highly accurate system simulations are needed for exploring architectural parameters to maximize the performance during the design phase. In this paper, we implement a simulator that considers all of the hardware components in SSD to assist in generating quantitatively accurate analysis when an algorithm or controller is realized. This simulator models the detailed characteristics of hardware components such as operation clock frequency and resource conflicts in order to represent SSD in great detail. In the experiments section, we verify the impacts of interface speed, page size, and other configuration parameters by using this cycle accurate simulator. These analysis results can then be used as raw data for optimization.

Efficient coordination of parallel threads of H.264/AVC decoder for performance improvement

The H.264/AVC decoder is a video codec standard that provides a high compression rate for a video. This decoder includes various algorithms to enhance the compression effect and consequently requires significant computational capability from processors to execute those algorithms. Since multi-core platforms are being widely used, research has been performed to improve the performance of the software H.264/AVC decoder by parallelizing it within multi-core platforms. However, there are many obstacles to parallelizing the existing decoder due to restrictions such as sequential execution, data subordination, and other limitations of the decoder. The parallelization of the decoder is often limited only to a subset of decoder functions. This paper analyzes such restrictions as the sequential execution and data subordination existent inside the H.264/AVC decoder and suggests a method for controlling the parallel execution of threads in order to bypass such restrictions. The experimental results show that the H.264/AVC decoder proposed parallelization technique achieves a 25% increase in speed compared with that of the existing parallelization approach.

Hierarchical use of heterogeneous flash memories for high performance and durability

The use of NAND flash memory for building permanent storage has been increasing in many embedded systems due to idiosyncrasies such as non-volatility and low energy consumption. The persistent requirements for high storage capacity have given rise to the increase of bit density per cell as in multi-level cells but this has come at the expense of performance and has resulted in degradation of durability. In this paper, we introduce a complementary approach to boost the performance and durability of MLC-based storage systems by employing a non-volatile buffer that temporarily holds the data heading to MLCs. We also propose algorithms to efficiently eliminate unnecessary write and erase operations in MLCs by performing a pre-merge in the buffer. Our experiments show that the proposed approach can decrease average response time by up to 4 times and increase durability by 4 times by adding only a small hardware cost.

A new mechanism for congestion and deadlock resolution

Efficient and reliable communication is essential for achieving high performance in a networked computing environment. Limited network resources bring about unavoidable competition among in-flight packets, resulting in network congestion and possibly deadlock. Many techniques have been proposed to improve performance by efficiently handling network congestion and deadlock. However, none of them provide an efficient way of accelerating the movement of packets involved in congestion onward to their destinations. In this paper, we propose a new mechanism for the detection and resolution of network congestion and deadlocks. The proposed mechanism is based on increasing the scheduling priority of packets involved in congestion and providing necessary resources for those packets to make forward progress. Simulation results show that the proposed technique outperforms previously proposed techniques by effectively dispersing network congestion.