Kyu-Nam Lim

Bit line coupling scheme and electrical fuse circuit for reliable operation of high density DRAM

Two design techniques are presented to improve the yield of high density DRAM product. One is bit line coupling (BLC) scheme and the other is electrical fuse (E-Fuse) circuit for reliable field programmable repair scheme. We obtain an improvement of 100 ms for the data retention time (tREF) using the BLC scheme. BLC scheme also improves the low VCC margin by 0.3 V and the RAS to CAS delay time (tRCD) by 1.5 ns. Differential current evaluation for the E-fuse implementation shows polysilicon fuse fail rate <10/sup -12/.

A 1.8 V 700 Mb/s/pin 512 Mb DDR-II SDRAM with on-die termination and off-chip driver calibration

A 1.8 V 700 Mb/s/pin 512 Mb DDR-II SDRAM is JEDEC standard compliant. With the hierarchical I/O line and local sensing, t/sub AA/ /t/sub RCD//t/sub RP/ of 3/3/3 at 533 Mb/s are achieved in the design. For signal integrity at 533 Mb/s, off-chip driver calibration and on-die termination are employed.

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-/spl mu/m CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with a non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.

Charge-transferred presensing and efficiently precharged negative word-line schemes for low-voltage DRAMs

A 256 Mb SDRAM is implemented with a 0.12 /spl mu/m technology to verify two circuit schemes suitable for mobile application. A charge transferred presensing is proposed to achieve fast low-voltage sensing and robust operation. With a precharge disabler for productivity, new negative word-line scheme is also proposed to bypass the majority of discharging current to VSS without switching control.