Jei-Hwan Yoo

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to < 100 mV even if all 4 ranks are refreshed every clock cycle consecutively.

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-NVM, application-oriented approaches using PRAM as main-memory or storage-class memory have been researched [2-3]. These studies suggest that noticeable merits can be achieved by using PRAM in improving power consumption, system cost, etc. However, relatively low chip density and insufficient write bandwidth of PRAMs are obstacles to better system performance. In this paper, we present an 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells [4]. When an external high voltage is applied, the write bandwidth can be extended as high as 133MB/s.

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

In mobile systems, the demand for the energy saving continues to require a low power memory sub-system. During the last decade, the floating-gate flash memory has been an indispensable low power memory solution. However, NOR flash memory has begun to show difficulties in scaling due to the devices reliability and yield issues. Over the past few years, phase-change random access memory (PRAM) has emerged as an alternative non-volatile memory (NVM) owing to its promising scalability and low cost process [1,2]. In this paper, a PRAM, implemented in a 58nm PRAM process with a low power double-data-rate nonvolatile memory (LPDDR2-N) interface, is presented [3].

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm/sup 2/ has been fabricated using 0.16 /spl mu/m four-poly, four-metal CMOS process technology.

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor

To verify three important circuit schemes suitable for DRAMs in mobile applications, a 1.8-V 128-Mb SDRAM was implemented with a 0.15-/spl mu/m technology. To achieve an ideal 33% efficiency, the double boosting pump uses two capacitors series connection at pumping phase, while they are precharged in parallel. The hybrid folded current sense amplifier together with a novel replica inverter connection improved power and speed performances. Also, a dual-referenced adjustment scheme for a temperature sensor was proposed to allow a very high accuracy in tuning. Without loss in productivity, the implemented dual-referenced searching technique achieved tuning error of less than /spl plusmn/2.5/spl deg/C.

A 31 ns Random Cycle VCAT-Based 4F

A functional 4F2 DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with more than twice turn-on current compared with the conventional recessed channel access transistor (RCAT). A new design methodology has been applied to accommodate 4F2 cell array, achieving both high performance and manufacturability. Especially, core block restructuring, word line (WL) strapping and hybrid bit line (BL) sense-amplifier (SA) scheme play an important role for enhancing AC performance and cell efficiency. A 50 Mb test chip was fabricated by 80 nm design rule and the measured random cycle time (tRC) and read latency (tRCD) are 31 ns and 8 ns, respectively. The median retention time for 88 Kb sample array is about 30 s at 90°C under dynamic operations. The core array size is reduced by 29% compared with conventional 6F2 DRAM.

^{2}

This paper describes several new circuit design techniques for low V/sub CC/ regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (/spl Delta/V/sub BL/) as well as the V/sub GS/ margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-/spl mu/m twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t/sub RAC/) of 28 ns at V/sub cc/=1.5 V and T=25/spl deg/C has been obtained.

DRAM With Manufacturability and Enhanced Cell Efficiency

This 32-bank 1 Gb DRAM features: (1) a merged bank architecture (MBA) that results in only 3% die area penalty for 32-bank operation; (2) a source-synchronous I/O interface (SSI) that achieves 1 GB/s bandwidth with low power consumption; (3) flexible block redundancy that allows freedom of repair to anywhere within each half-Gb array; and (4) extended small swing read and single-I/O line driving write which result in 30% power reduction. The DRAM chip is implemented in a 0.16 /spl mu/m twin-well CMOS process.

Low-voltage, high-speed circuit designs for gigabit DRAMs

A 1.8V 128Mb SDRAM is implemented for low current mobile applications with a 0.15/spl mu/m technology. The double boosting pump and hybrid current sense amplifier schemes are optimized for the low voltage regime with high pumping efficiency and stable I-to-V gain, respectively. A temperature sensor together with the binary weighted adjustment technique allow a very accurate implementation without loss in productivity.

A 32-bank 1 Gb DRAM with 1 GB/s bandwidth

A 256 Mb SDRAM is implemented with a 0.12 /spl mu/m technology to verify two circuit schemes suitable for mobile application. A charge transferred presensing is proposed to achieve fast low-voltage sensing and robust operation. With a precharge disabler for productivity, new negative word-line scheme is also proposed to bypass the majority of discharging current to VSS without switching control.