Kyungjun Cho

Design optimization of high bandwidth memory (HBM) interposer considering signal integrity

As total system bandwidth increased, memory industry has been imposed to satisfy its requirements. At last, innovative next generation memory named high bandwidth memory (HBM) with extremely fine micro-bump pitch of its bottom die is introduced for terabytes/s bandwidth graphics module. To establish HBM based graphics module, it becomes essential to fabricate silicon interposer due to its capability to process narrow signal width and space. Silicon based HBM interposer becomes the key solution to mitigate bandwidth bottleneck of graphics module for high computing system. To design HBM interposer successfully, the signal optimization of HBM interposer channels must be preceded thoroughly. In this paper, design optimization of top metal signals of HBM interposer considering routing feasibility is proposed. In order to analyze channel performance to determine optimal line width and space, frequency domain and time domain simulation are conducted respectively. All the proposed signals in HBM interposer are analyzed by comparing eye-opening voltage and timing jitter with 3D electromagnetic (EM) simulation results. Based on this proposed optimization design, not only HBM interposer can be applied to achieve high bandwidth with a less signal distortion but also it can be designed on the basis of a limited routing area.

Measurement and Analysis of Glass Interposer Power Distribution Network Resonance Effects on a High-Speed Through Glass Via Channel

In this paper, we measured and analyzed glass interposer power distribution network (PDN) resonance effects on a high-speed through glass via (TGV) channel for the first time. To verify the glass interposer PDN resonance effects on the TGV channel, glass interposer test vehicles were fabricated. With these test vehicles, glass interposer PDN impedance, channel loss, far-end crosstalk, and eye diagram are measured. Based on these measurements, glass interposer PDN resonance effects on the signal integrity of the high-speed TGV channel are analyzed. Due to low loss of the glass substrate, sharp high PDN impedance peaks are generated at the resonance frequencies. High PDN impedance peaks at the PDN resonance frequencies, which affect return current of the TGV channel, increase channel loss, crosstalks, and PDN noise coupling in the frequency domain and degrade eye diagram in the time domain. To suppress these glass interposer PDN resonance effects, a ground shielded-TGV scheme is proposed. The proposed ground shielded-TGV scheme includes two ground TGVs 200 μm away from the signal TGV considering the design rules and includes package ground underneath the glass interposer. Effectiveness of the suggested grounding scheme on the resonance effects suppression is verified with three-dimensional electromagnetic simulation. The proposed shielded-TGV design successfully suppressed the glass interposer PDN resonance effects that results in the suppression of insertion loss, shielding of the crosstalk, and improvement of the eye diagram of the high-speed TGV channel.

Design and Analysis of Power Distribution Network (PDN) for High Bandwidth Memory (HBM) Interposer in 2.5D Terabyte/s Bandwidth Graphics Module

A semiconductor industry has been encountered a memory bandwidth bottleneck toward a high density and high bandwidth system. In order to overcome those limitations, a 3D stacked high bandwidth memory (HBM) based on a through silicon via (TSV) and fine pitch interposer technology is lately introduced. By adopting this structure, thousands numbers of input/output (I/O) channels with a fine pitch can be integrated on HBM interposer which enables a terabyte/s bandwidth system. On the HBM interposer, significant numbers of I/O are integrated and they tend to operate at the same time which leads to severe simultaneous switching noise (SSN). When SSN occurs, the performance of system can be heavily degraded. Total SSN is strongly related to the self-noise and transfer-noise. In this point of view, a proper PDN design to manage transfer noise which is closely related to transfer-impedance must be taken into account. The analysis of power distribution network (PDN) impedance of HBM interposer must be performed since it generally affects power supply to the chips as well as signal integrity (SI). In this paper, HBM interposer with five layers is designed to analyze PDN. For PDN impedance analysis, Z-parameters depending on the various physical dimensions are simulated and compared. PDN impedance of HBM interposer is simulated and analyzed in the interest of frequency range dominated by interposer PDN. In order to suppress SSN, we suggest a metal-insulator-metal (MIM) de-cap scheme which can be commonly available for HBM interposer to reduce PDN impedance. Based on the designed physical dimension and material properties of HBM interposer, we successfully shows the suppression of SSN.

Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics module

Recently, IT trends such as big data, cloud computing, internet of things (IoT), 3D visualization, network, and so on demand terabyte/s bandwidth computer performance in a graphics card. In order to meet these performance, terabyte/s bandwidth graphics module using 2.5D-IC with high bandwidth memory (HBM) technology has been emerged. Due to the difference in scale of interconnect pitch between GPU or HBM and package substrate, the HBM interposer is certainly required for terabyte/s bandwidth graphics module. In this paper, the electrical performance of the HBM interposer channel in consideration of the manufacturing capabilities is analyzed by simulation both the frequency- and time-domain. Furthermore, although the silicon substrate is most widely employed for the HBM interposer fabrication, the organic and glass substrate are also proposed to replace the high cost and high loss silicon substrate. Therefore, comparison and analysis of the electrical performance of the HBM interposer channel using silicon, organic, and glass substrate are conducted.

Power distribution network (PDN) design and analysis of a single and double-sided high bandwidth memory (HBM) interposer for 2.5D Terabtye/s bandwidth system

A 3-D stacked high bandwidth memory (HBM) becomes a promising solution to satisfy the memory bandwidth for the processor. Due to its unique memory architecture that consists of tremendous number of input/output (I/O), it is inevitable to employee Silicon based interposer. Therefore, power distribution network (PDN) design and analysis of HBM interposer becomes one of the important step to guarantee the performance of an entire memory interface. Since the back end of line (BEOL) process technology of a semiconductor industry is applied for HBM interposer, the control of a metal density and the management of wafer warpage are required. Therefore, we designed and analyzed meshed and grid type of PDN for HBM interposer because of the limit of a metal density. In addition, we also designed and analyzed PDN both a single- and double-sided interposer. Because, a double-sided interposer has an advantage of a warpage management compared to a single-sided interposer. For the suppression of simultaneous switching noise (SSN), PDN impedance with a decoupling capacitor scheme must be properly analyzed. In this paper, a single- and double-sided HBM interposer is designed with the five layers and six layers respectively to analyze PDN impedance including though-Silicon-via (TSV). PDN impedance of HBM interposer is simulated and analyzed in the frequency range from 100 MHz to 20 GHz. Based on the designed HBM interposer, we shows the great potential of HBM interposer in terms of the reduction of PDN impedance to suppress SSN with a metal-insulator-metal (MIM) decoupling capacitor.

Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC

In this paper, crosstalk-included eye-diagram of high-speed interposer channels are estimated and investigated. To analyze the crosstalk effect of various interposer channels, silicon, organic, and glass substrates are compared under the same physical structure and dimensions. Moreover, crosstalk-included eye-diagrams are estimated in short time with high accuracy using 8 worst input cases. The estimated crosstalk-included eye-diagrams are analyzed at data rate of 1 and 2 Gbps.

Eye-diagram estimation and analysis of High-Bandwidth Memory (HBM) interposer channel with crosstalk reduction schemes on 2.5D and 3D IC

In this paper, eye-diagrams of High-Bandwidth Memory (HBM) interposer channel with crosstalk reduction schemes on 2.5D / 3D IC are estimated and analyzed. As data rate increases and metal-to-metal space decreases to achieve higher system bandwidth, crosstalk effects degrade the signal integrity. Therefore, estimation and reduction of the crosstalk effects are essential on HBM interposer channel. In order to estimate crosstalk effects in short time with high accuracy, PDA-based estimation method is proposed. In addition to the proposed method, wide space and guard trace with ground vias structures are suggested and compared based on the estimated eye-diagrams. With the estimated eye-diagrams, voltage fluctuation on DC levels due to the crosstalk effects can be analyzed. Worst and statistical eye-diagrams of interposer channels including crosstalk effects are estimated. Since the proposed method needs only output and crosstalk response of the channel, the proposed method can be applied to multiple wide I/O channels.

Signal Integrity of Bump-Less High-Speed through Silicon Via Channel for Terabyte/s Bandwidth 2.5D IC

In this paper, a bump-less high-speed through silicon via (TSV) channel is proposed for terabyte/s bandwidth 2.5D IC. The signal integrity of the proposed channel is analyzed based on the frequency and time domain simulation. To analyze the signal integrity of the proposed channel minutely, the proposed channel and the conventional channel are simulated and compared respectively. Moreover, unlike the conventional channel, the signal integrity of the proposed channel is significantly affected by the coupling pads capacitance. Therefore, the proposed channel performance is investigated with different coupling pads capacitances.

Miniaturized and high-performance RF packages with ultra-thin glass substrates

Abstract Advanced RF packages are demonstrate with active (low-noise amplifier, RF switch) and passive integration in ultra-thin 3D glass packages with miniaturization and enhanced performance. The novelty of this RF packages is three-fold: 1) Ultra-thin 100 μm glass, 2) Double-side thinfilm RF circuits interconnected with Through-Package Vias (TPVs), and 3) Direct assembly of the glass-core package to the board with Land Grid Array (LGA) connections. An innovative double-via process, starting from prefabricated vias in bare glass, polymer filling and via drilling, is utilized for a robust and high-yield substrate fabrication process. Scalable and low-cost panel laminate processes are utilized to form the RF circuits on the build-up layers. The performance benefits are demonstrated through interconnect loss, impedance match, electrical gain and noise figure measurements. Compared to existing RF substrates, the glass substrates show 2.5X miniaturization in substrate thickness with extensibility to thinner substrates.

Design and analysis of receiver channels of glass interposer for dual band Wi-Fi front end module (FEM)

In this paper, we design and analyze the receiver channel of a glass interposer for a dual band Wi-Fi front end module (FEM). In RF systems, a RF sensitivity is the most important specification for a system performance and reliability. To guarantee a target RF sensitivity of the RF system, it is important to maintain a 50 Ohm impedance matching for RF channels. The 50 Ohm impedance matching of various transmission line structures is completely conducted for each layer of the glass interposer in a low band (2.4GHz – 2.5GHz) and high band (4.9GHz – 5.85GHz) respectively. Channel types for each layer are determined considering design rules and constraints. Moreover, we locate ground TGVs near signal TGVs as close as possible to suppress a ground-ground cavity resonance effect in the low band and high band. In order to test a suppression of the ground-ground cavity resonance, simulations that compare pitches between a ground TGV and signal TGV are conducted. Design considerations of receiver channels were analyzed and characterized by simulation results of channel insertion losses.