Sumin Choi

Preparation of polythiophene LB films and their gas sensitivities by the ouartz crystal microbalance

Abstract The gas sensitivity of polythiophene LB film was investigated. As polythiophene has the conjugated double bond, the potential applications to the various devices using its conducting property have been proposed. The Langmuir-Blodgett(LB) technique has been used to manipulate conducting polymers to multilayer thin films with well defined structures and ordered molecular orientations. In this study, we have synthesized the polythiophene derivatives such as poly(octyl thiophene)(POT), poly(propanoate thiophene)(PEPT) and poly(decanoate thiophene)(PEDT), and observed their behaviors at the air/water interface. For the preparation of polythiophene LB films with good quality, we have used the mixed monolayer with surface active materials like octadecylamine(ODA) and controlled the subphase conditions. Also, for the application to the sensing materials, we have tested the gas sensitivities of polythiophene derivatives LB films to NO 2 gas by the quartz crystal microbalance(QCM).

Design optimization of high bandwidth memory (HBM) interposer considering signal integrity

As total system bandwidth increased, memory industry has been imposed to satisfy its requirements. At last, innovative next generation memory named high bandwidth memory (HBM) with extremely fine micro-bump pitch of its bottom die is introduced for terabytes/s bandwidth graphics module. To establish HBM based graphics module, it becomes essential to fabricate silicon interposer due to its capability to process narrow signal width and space. Silicon based HBM interposer becomes the key solution to mitigate bandwidth bottleneck of graphics module for high computing system. To design HBM interposer successfully, the signal optimization of HBM interposer channels must be preceded thoroughly. In this paper, design optimization of top metal signals of HBM interposer considering routing feasibility is proposed. In order to analyze channel performance to determine optimal line width and space, frequency domain and time domain simulation are conducted respectively. All the proposed signals in HBM interposer are analyzed by comparing eye-opening voltage and timing jitter with 3D electromagnetic (EM) simulation results. Based on this proposed optimization design, not only HBM interposer can be applied to achieve high bandwidth with a less signal distortion but also it can be designed on the basis of a limited routing area.

The characteristics of metallophthalocyanine mono-, multilayer and application to the gas sensor for NO2

Abstract The preparation of Langmuir-Blodgett(LB) films of metallophthalocyanines(MPcs) with symmetric octa(2-ethylhexyloxy) side chain and their possible use in gas sensing device were examined. Complexed central metal ion, which include copper, lead, platinum, cobalt and dihydrogen was varied and 2-ethylhexyl chains were substituted at both 2- and 3-position of each bingo ring in the phthalocyanine compound. Mono- and multilayer LB films were transferred to a 6 MHz quartz crystal microbalance(QCM) by vertical dipping method. The interaction or responses of film coated QCM to NO 2 have been tested, and after the heat treatment, the good recovery efficiencies were achieved for repeated use.

A Wideband On-Interposer Passive Equalizer Design for Chip-to-Chip 30-Gb/s Serial Data Transmission

In this paper, a novel on-interposer passive equalizer is proposed for chip-to-chip high-speed data transmission on the silicon-based on-interposer channel. The proposed equalizer uses the parasitic resistance and inductance of the on-interposer shunt metal lines to produce the high-pass filter. This filter enables the proposed equalizer to exhibit wideband channel equalization and low power-consumption. Based on the equivalent-circuit model of the proposed on-interposer passive equalizer, the physical dimensions of the equalizer are optimized for 30-Gb/s serial data transmission. The performance of the proposed equalizer with the optimized dimensions was successfully demonstrated by both frequency- and time-domain measurements at data rates of up to 30 Gb/s. In addition, a compact on-interposer passive equalizer was designed for the wide I/O interposer using the same mechanism. The improved quality of serial data transmission in the equalized wide I/O on-interposer channel was successfully verified by simulations at data rates of up to 10 Gb/s.

Crosstalk included eye diagram estimation of high-speed and wide I/O interposer channel for 2.5D / 3D IC

In this paper, crosstalk included eye diagram of high-speed and wide I/O interposer channels are simulated and analyzed. To analyze the crosstalk effect of various substrate channels, silicon, glass, and organic interposers are simulated and compared under the same physical dimensions. In addition, crosstalk included eye diagrams are accurately estimated in short time using 8 worst case input signals. The estimated eye diagrams are investigated at data rate of 10 Gbps.

Through Silicon Via (TSV) Defect Modeling, Measurement, and Analysis

Through silicon via (TSV)-based 3-D integrated circuit has introduced the solution to limitlessly growing demand on high system bandwidth, low power consumption, and small form factor of electronic devices. As the system design aims for higher performance, the physical dimensions of the channels are continuously decreasing. With TSV diameter of less than 10 μm and pitch of several tens of micrometers, the I/O count has increased up to the order of tens of thousands for wide bandwidth data transmission. However, without highly precise fabrication process, such small structures are susceptible to a variety of defects. For the first time, in this paper, we propose a noninvasive defect analysis method for high-speed TSV channel. With designed and fabricated test vehicles, the proposed method is demonstrated with S-parameter and time-domain reflectometry measurement results. In addition, we present equivalent circuit models of TSV daisy-chain structures, including the circuit components for open defect and short defect. With characterized dominant factors in each frequency range, S11 is analyzed to distinguish and locate the defects by the amount of capacitance, resistance, and inductance that the signal experiences. S-parameter measurement sufficiently allows high-frequency defect analysis of TSV channel without destroying the test sample. We experimentally verified the accuracy of the suggested model by comparing the S-parameter results from circuit simulations and measurements. Finally, the model is modified to discuss the effects of open defect and short defect on the electrical characteristics of TSV channel.

Design and Analysis of Power Distribution Network (PDN) for High Bandwidth Memory (HBM) Interposer in 2.5D Terabyte/s Bandwidth Graphics Module

A semiconductor industry has been encountered a memory bandwidth bottleneck toward a high density and high bandwidth system. In order to overcome those limitations, a 3D stacked high bandwidth memory (HBM) based on a through silicon via (TSV) and fine pitch interposer technology is lately introduced. By adopting this structure, thousands numbers of input/output (I/O) channels with a fine pitch can be integrated on HBM interposer which enables a terabyte/s bandwidth system. On the HBM interposer, significant numbers of I/O are integrated and they tend to operate at the same time which leads to severe simultaneous switching noise (SSN). When SSN occurs, the performance of system can be heavily degraded. Total SSN is strongly related to the self-noise and transfer-noise. In this point of view, a proper PDN design to manage transfer noise which is closely related to transfer-impedance must be taken into account. The analysis of power distribution network (PDN) impedance of HBM interposer must be performed since it generally affects power supply to the chips as well as signal integrity (SI). In this paper, HBM interposer with five layers is designed to analyze PDN. For PDN impedance analysis, Z-parameters depending on the various physical dimensions are simulated and compared. PDN impedance of HBM interposer is simulated and analyzed in the interest of frequency range dominated by interposer PDN. In order to suppress SSN, we suggest a metal-insulator-metal (MIM) de-cap scheme which can be commonly available for HBM interposer to reduce PDN impedance. Based on the designed physical dimension and material properties of HBM interposer, we successfully shows the suppression of SSN.

Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics module

Recently, IT trends such as big data, cloud computing, internet of things (IoT), 3D visualization, network, and so on demand terabyte/s bandwidth computer performance in a graphics card. In order to meet these performance, terabyte/s bandwidth graphics module using 2.5D-IC with high bandwidth memory (HBM) technology has been emerged. Due to the difference in scale of interconnect pitch between GPU or HBM and package substrate, the HBM interposer is certainly required for terabyte/s bandwidth graphics module. In this paper, the electrical performance of the HBM interposer channel in consideration of the manufacturing capabilities is analyzed by simulation both the frequency- and time-domain. Furthermore, although the silicon substrate is most widely employed for the HBM interposer fabrication, the organic and glass substrate are also proposed to replace the high cost and high loss silicon substrate. Therefore, comparison and analysis of the electrical performance of the HBM interposer channel using silicon, organic, and glass substrate are conducted.

A fast and accurate statistical eye-diagram estimation method for high-speed channel including non-linear receiver buffer circuit

In this work, a fast and accurate statistical eye-diagram estimation method for high-speed single-ended channel including non-linear pseudo differential receiver buffer circuit is proposed. For accurate estimation, the analytical model of the pseudo differential receiver buffer output voltage that includes impacts of external noises is derived based on piece-wise linear approximated MOS I-V curves. Moreover, the calculation based on compact input set whose components are possible receiver input waveforms for one unit interval enables the proposed method to calculate BER within short time. Accuracy and fast estimation time of the proposed method are successfully verified by comparing to the transient simulation results.

A compact on-interposer passive equalizer for chip-to-chip high-speed data transmission

In this paper, a new compact on-interposer passive equalizer was proposed for chip-to-chip high-speed data transmission on the silicon-based on-interposer channel. The proposed equalizer uses the parasitic resistance and inductance of the coil-shaped on-interposer shunt metal line structure to produce the high-pass filter for loss compensation. This results in wide-band channel equalization and low power-consumption. Moreover, the compact coil-shaped structure of the proposed equalizer allows for wide I/O and high adjustability. The remarkable performance of the proposed compact on-interposer passive equalizer is successfully demonstrated by a frequency-and time-domain simulation of up to 10 Gbps.