Subin Kim

Measurement and Analysis of Glass Interposer Power Distribution Network Resonance Effects on a High-Speed Through Glass Via Channel

In this paper, we measured and analyzed glass interposer power distribution network (PDN) resonance effects on a high-speed through glass via (TGV) channel for the first time. To verify the glass interposer PDN resonance effects on the TGV channel, glass interposer test vehicles were fabricated. With these test vehicles, glass interposer PDN impedance, channel loss, far-end crosstalk, and eye diagram are measured. Based on these measurements, glass interposer PDN resonance effects on the signal integrity of the high-speed TGV channel are analyzed. Due to low loss of the glass substrate, sharp high PDN impedance peaks are generated at the resonance frequencies. High PDN impedance peaks at the PDN resonance frequencies, which affect return current of the TGV channel, increase channel loss, crosstalks, and PDN noise coupling in the frequency domain and degrade eye diagram in the time domain. To suppress these glass interposer PDN resonance effects, a ground shielded-TGV scheme is proposed. The proposed ground shielded-TGV scheme includes two ground TGVs 200 μm away from the signal TGV considering the design rules and includes package ground underneath the glass interposer. Effectiveness of the suggested grounding scheme on the resonance effects suppression is verified with three-dimensional electromagnetic simulation. The proposed shielded-TGV design successfully suppressed the glass interposer PDN resonance effects that results in the suppression of insertion loss, shielding of the crosstalk, and improvement of the eye diagram of the high-speed TGV channel.

Design and Analysis of Power Distribution Network (PDN) for High Bandwidth Memory (HBM) Interposer in 2.5D Terabyte/s Bandwidth Graphics Module

A semiconductor industry has been encountered a memory bandwidth bottleneck toward a high density and high bandwidth system. In order to overcome those limitations, a 3D stacked high bandwidth memory (HBM) based on a through silicon via (TSV) and fine pitch interposer technology is lately introduced. By adopting this structure, thousands numbers of input/output (I/O) channels with a fine pitch can be integrated on HBM interposer which enables a terabyte/s bandwidth system. On the HBM interposer, significant numbers of I/O are integrated and they tend to operate at the same time which leads to severe simultaneous switching noise (SSN). When SSN occurs, the performance of system can be heavily degraded. Total SSN is strongly related to the self-noise and transfer-noise. In this point of view, a proper PDN design to manage transfer noise which is closely related to transfer-impedance must be taken into account. The analysis of power distribution network (PDN) impedance of HBM interposer must be performed since it generally affects power supply to the chips as well as signal integrity (SI). In this paper, HBM interposer with five layers is designed to analyze PDN. For PDN impedance analysis, Z-parameters depending on the various physical dimensions are simulated and compared. PDN impedance of HBM interposer is simulated and analyzed in the interest of frequency range dominated by interposer PDN. In order to suppress SSN, we suggest a metal-insulator-metal (MIM) de-cap scheme which can be commonly available for HBM interposer to reduce PDN impedance. Based on the designed physical dimension and material properties of HBM interposer, we successfully shows the suppression of SSN.

Power distribution network (PDN) design and analysis of a single and double-sided high bandwidth memory (HBM) interposer for 2.5D Terabtye/s bandwidth system

A 3-D stacked high bandwidth memory (HBM) becomes a promising solution to satisfy the memory bandwidth for the processor. Due to its unique memory architecture that consists of tremendous number of input/output (I/O), it is inevitable to employee Silicon based interposer. Therefore, power distribution network (PDN) design and analysis of HBM interposer becomes one of the important step to guarantee the performance of an entire memory interface. Since the back end of line (BEOL) process technology of a semiconductor industry is applied for HBM interposer, the control of a metal density and the management of wafer warpage are required. Therefore, we designed and analyzed meshed and grid type of PDN for HBM interposer because of the limit of a metal density. In addition, we also designed and analyzed PDN both a single- and double-sided interposer. Because, a double-sided interposer has an advantage of a warpage management compared to a single-sided interposer. For the suppression of simultaneous switching noise (SSN), PDN impedance with a decoupling capacitor scheme must be properly analyzed. In this paper, a single- and double-sided HBM interposer is designed with the five layers and six layers respectively to analyze PDN impedance including though-Silicon-via (TSV). PDN impedance of HBM interposer is simulated and analyzed in the frequency range from 100 MHz to 20 GHz. Based on the designed HBM interposer, we shows the great potential of HBM interposer in terms of the reduction of PDN impedance to suppress SSN with a metal-insulator-metal (MIM) decoupling capacitor.

Design and analysis of on-interposer active power distribution network for an efficient simultaneous switching noise suppression in 2.5D IC

Simultaneous switching noise (SSN) occurs when clock synchronized core circuits switch simultaneously. Furthermore, a huge amount of the SSN generated by simultaneous switching current (SSC) with high power distribution network (PDN) impedance at anti-resonance can cause electromagnetic interference (EMI) problems and logic failure. In multi-core processors, the spectrum of SSC is varied by power management techniques such as dynamic voltage and frequency scaling (DVFS). However, conventional PDN cannot respond to these various SSC spectrum due to its passive characteristics. In this paper, an externally controllable on-interposer decoupling capacitance scheme, namely on-interposer active PDN, is proposed to efficiently suppress the SSN in 2.5D IC. The proposed scheme designed on the active silicon interposer can shift the frequency of the PDN anti-resonance peak with on-interposer decoupling capacitors controlled by external switching operation based on monitored SSN voltage. To verify the proposed scheme, it is modeled and analyzed in the frequency and time domain simulations. We have demonstrated that an efficient SSN suppression is achieved by obtaining the optimum on-interposer decoupling capacitance and the maximum ratio of the SSN suppression was 31.3%.

Electromagnetic Bandgap Design for Power Distribution Network Noise Isolation in the Glass Interposer

2.5-Dimensional integration based on glass interposer technology is a potential means of achieving high-bandwidth and high-integration density electrical systems. Ultra-low loss glass substrate enables high-frequency signaling but this low loss substrate is vulnerable to the noise suppression in the power distribution network (PDN). Electromagnetic Band-gap (EBG) structures in the PDN are well-known techniques to suppress the PDN noise. We first designed and fabricated EBG structures in the glass interposer PDN and analyzed effectiveness of these EBG structures for the noise suppression in the PDN.

Audio frequency ground integrity modeling and measurement for a TDMA smartphone system

In this paper, we first propose a ground network model of an arbitrary shaped multi-layer printed circuit board (PCB)/chassis for accurate and efficient analysis of audio frequency ground noise coupled from a time division multiple access (TMDA) RF power amplifier (PA) to an audio circuit in a smartphone system. We designed test vehicles with varied extent in the ground noise coupling. We successfully verified the proposed model by comparing the ground noise coupling levels obtained from the model, 3-D electromagnetic (EM) simulation and measurement in time and frequency domain. We further discussed the performance of the proposed model by comparing the accuracy of its transfer ground impedance (ZG12) and analysis time with those of from the EM simulation. The proposed model showed high performance with the ZG12 agreed 91.7 % with the EM simulation, and the analysis time 95.5 % reduced compared to the simulation.

Power/ground noise coupling comparison and analysis in silicon, organic and glass interposers

In this paper, we compare and analyze power/ground noise coupling in silicon, organic and glass interposers. We first compare the power/ground noise coupling of each interposer by analyzing transfer impedances of power distribution networks (PDNs). Due to low loss of the organic and glass substrates, at certain frequencies, transfer impedances increase dramatically and. In order to analyze the effects of the power/ground noise propagation in the PDN and coupling to through via channel we induced clock signals to each interposers aggressor through via channel with data rate corresponds to the PDN (1,0)/(0,1) resonance frequency to load the power/ground noises in the PDN. We monitored the coupled voltages in the PDNs and compared eye-diagrams of the victim through via channels. Due to the low loss of the glass substrate, glass interposers turned out to be most vulnerable to the power/ground noise. We suppressed PDN transfer impedance of the glass interposer using decoupling capacitors and electromagnetic band gap structure.