Kyu-Charn Park

Charge-trapping memory cell of SiO2∕SiN∕high‐k dielectric Al2O3 with TaN metal gate for suppressing backward-tunneling effect

We present a device structure of SiO2∕SiN∕Al2O3 (SANOS) with tantalum nitride (TaN) metal gate. When TaN metal gate is applied for the SANOS structure instead of commonly used n-type poly-silicon, the unwanted backward Fowler–Nordheim tunneling current of electron through the top oxide is significantly suppressed owing to its higher work function and better compatibility with high-k dielectrics. As a result, the program∕erase speed is significantly improved and the erase threshold voltage (VTH) can be obtained to be negative voltage of −3.5V.

Performance characteristics of SOI DRAM for low-power application

Process integration of cell capacitors that can circumvent the usual difficulties of large topographic height difference and high-temperature process are presented. A 16 Mbit silicon-on-insulator (SOI) DRAM with a 0.3 /spl mu/m design rule is successfully fabricated and analyzed for processing integrity and circuit performance based on process integration of the cell capacitor using the pattern-bonded SOI (PBSOI) technology. Measurements for the strobe access time (tRAC) acid the operation current (I/sub ccl/) show significant improvement (over 25%) for the SOI DRAM compared to those for the 16 Mbit bulk counterpart with the same circuit and layout. On the transistor side, ultra-low-voltage transistor technology using the body bias control schemes is also implemented and investigated. Devices with small leakage current and almost ideal subthreshold swing are obtained. The results give us guidance for transistor and process schematics for low-voltage DRAM application.

Fin-type field-effect transistor NAND flash with nitride/silicon nanocrystal/nitride hybrid trap layer

The effects of trap layer on NAND flash performances have been described in this paper. In order to overcome the slower programming speed of the discrete trap memory than conventional floating-gate device, nitride and silicon nanocrystal have been assembled together so as to provide the higher trap density for the improved device performance. This hybrid trap layer technology has been applied to the fin-type field-effect transistor (FinFET) NAND flash, and the results show ~5 V of program/erase window with reasonable device reliabilities.

Improved post-cycling characteristic of FinFET NAND Flash

In this paper, SONOS type FinFET device has been fabricated and characterized for the NAND flash application. Pre- and post-cycling characteristics are mainly studied both for the FinFET and planar device, with respect to the memory cell performance and device reliability. It has been demonstrated that the performance improvement of the FinFET is maintained after cycling stress, and most importantly, the superior bake retention characteristic of FinFET device is observed after cycling stress compared to the planar device

A 0.15 /spl mu/m NAND flash technology with 0.11 /spl mu/m/sup 2/ cell size for 1 Gbit flash memory

A new 1 Gb NAND flash technology with high-aspect-ratio floating gate, tungsten bit line and poly-Si source line has been developed. It is fabricated using 0.15 /spl mu/m photolithography, shallow trench isolation (STI), highly selective gate etching, damascene and chemical-mechanical polishing (CMP) processes. Since thick poly-Si is deposited and its sidewall has an inclined profile by anisotropic etching, narrow floating gate space (/spl sim/80 nm) under the design rule and a high coupling ratio (/spl sim/0.75) are obtained. To interconnect the NAND cell array, the poly-Si source is connected to every string as a common line and the tungsten bit line is damascened over the entire string. These double-layer interconnections lead to simple process and reduced steps. Thus, for the first time, a prototype 1 Gb NAND flash memory with an extremely small cell size of 0.11 /spl mu/m/sup 2/ has been achieved.

A 70nm NOR flash technology with 0.049 /spl mu/m/sup 2/ cell size

A 70nm NOR flash technology has been for the first time developed with a cell size of 0.0494m, which is the smallest size of NOR flash cell, for high density memory of mobile application. The operation of 0.049PM cell transistor is successfully achieved with three key technologies such as an optimized Self-Aligned Poly (SAP) structure with top corner rounding trench structure, a cell drain contact process by ArF photo lithographic tool, and a cell transistor with a gate length of 120nm.

70nm NAND flash technology with 0.025 /spl mu/m/sup 2/ cell size for 4Gb flash memory

A 4 Gb NAND flash memory with a 70 nm design rule is developed for mass storage applications. The cell size is 0.025 /spl mu/m/sup 2/, which is the smallest value ever reported. For the integration, an ArF lithography process along with resolution enhancing techniques was utilized, and poly-Si/W gate technology with an optimized re-oxidation process was implemented.

Highly manufacturable 1 Gb NAND flash using 0.12 /spl mu/m process technology

An 1 Gb NAND flash memory has been successfully developed by integrating new technologies, inverse narrow-width effect (INWE) suppression scheme, 32-cell NAND flash combined with the scaling-down of tunnel oxide, inter-poly ONO, and gate poly re-oxidation. It is implemented using KrF photolithography along with a resolution enhancing technique, the planarized surface by etch-back and CMP processes, highly selective contact etching and nonoverlapped dual damascene metallization. Thus, for the first time, a 1 Gb NAND flash memory with mass-producible chip size of 132 mm/sup 2/, lower Vcc operation below 1.8 V and lower power consumption, has been obtained.

Advanced integration technology for a highly scalable SOI DRAM with SOC (Silicon-On-Capacitors)

A fully planarized 16 Mb SOI DRAM has been successfully fabricated featuring pattern-bonded SOI (PBSOI), CMP processes, STI (Shallow Trench Isolation) and the silicon-on-capacitor (SOC) structure with 0.3 um technology using i-line lithography. The floating body effects of cell and peripheral SOI transistors are suppressed by the LIF (Local Implantation post Field oxidation) and halo implantation. The fully planarized process with SOC structure is established for multi-gigabit DRAM and embedded memory devices.

Highly manufacturable 90 nm NOR flash technology with 0.081 /spl mu/m/sup 2/ cell size

A manufacturable 90 nm NOR Flash technology has been developed with extremely small cell size of 0.081/spl mu/m/sup 2/, which is the smallest cell size of NOR cell, for high density code storage memory featuring with low voltage operation. The small cell size of 0.081/spl mu/m/sup 2/ is successfully achieved with three key main technologies such as an advanced KrF lithography with off-axis illumination system, appropriate dielectric thin film and junction scaling and optimized oxidation encroachment of inter-poly oxide nitride oxide (ONO) and tunnel oxide.