L. Di Cioccio

Silicon carbide on insulator formation by the Smart-Cut® process

Abstract For the first time silicon carbide on insulator structures (SiCOI) were achieved by the Smart-Cut® process. These structures were formed on polycrystalline SiC and on silicon substrates. The technological solutions used and the structures obtained are presented in this paper.

Engineered substrates for future More Moore and More than Moore integrated devices

In 1991, M. Bruel (1) invented and patented the Smart Cut technology to fabricate Silicon On Insulator (SOI) substrates. The process relies on the transfer of a high quality single crystal layer from one wafer to another: implantation of gaseous ions in a single crystal wafer, direct bonding on a stiffener and splitting (Fig 1). The invention of this SOI process combined with the entrepreneurship of SOITEC paved the way to high quality SOI substrates mass production. Today, SOI is a mature product (up to 300mm diameter) and now developments are focused on the integration of new materials and functionalities in order to improve device performances and enlarge the application spectrum.

Overview of recent direct wafer bonding advances and applications

Direct wafer bonding processes are being increasingly used to achieve innovative stacking structures. Many of them have already been implemented in industrial applications. This article looks at direct bonding mechanisms, processes developed recently and trends. Homogeneous and heterogeneous bonded structures have been successfully achieved with various materials. Active, insulating or conductive materials have been widely investigated. This article gives an overview of Si and SiO2 direct wafer bonding processes and mechanisms, silicon-on-insulator type bonding, diverse material stacking and the transfer of devices. Direct bonding clearly enables the emergence and development of new applications, such as for microelectronics, microtechnologies, sensors, MEMs, optical devices, biotechnologies and 3D integration.

Investigation of stress induced voiding and electromigration phenomena on direct copper bonding interconnects for 3D integration

We investigate for the first time the reliability of the direct copper bonding process. Electromigration (EM) and Stress Induced Voiding (SIV) tests are performed on intensive 30000 daisy chains and emphasize the good behaviour facing the risk of reliability issues in Cu/Cu bonded interconnects achieved by a direct low temperature (200°C) bonding. Furthermore, a comparison between stand alone and bonded device shows that the metallic bonding interfaces do not impact on the failure mechanism during EM tests.

YBaCuO-based multilayers for optoelectronic devices

Abstract YBaCuO (YBCO) based multilayers have been deposited independently by three techniques: laser ablation, inverted cylindrical target sputtering and on-axis planar d.c. magnetron sputtering. The last technique is used to cover uniformly R-plane sapphire and LaAlO3 2 in wafers with YBCO or multilayers to produce optoelectronic devices such as IR detectors. Very thin (about 3 nm) yttria-stabilized zirconia and MgO dielectric films have been studied as tunnel barriers for making such high T c tunnel junctions.

From epitaxy to converters topologies what issues for 200 mm GaN/Si?

Energy is one of the main societal challenges of the 21th century. With the growth of population and cities, CO2 emission reduction, efficiency improvements especially in transportation modes will have to be enhanced. Cost will the main driver of power devices. This paper reviews the developments at CEA-Leti in power electronics. A complete GaN on 200 mm line has been implemented. For each stage of device realization a discussion of the issues will be done.

Deposition, evaluation and control of 4H and 6H SiC epitaxial layers for device applications

Abstract We report an experimental investigation of the deposition, optical characterization and electrical properties of 6H and 4H-SiC epitaxial layers grown by atmospheric pressure chemical vapor deposition in a home made ‘cold wall’ reactor. From a growth kinetic study performed using our deposition conditions (1 atm, 1700 K) we show that our results can be very well explained using a stagnant layer model. We also underline that the decrease of the growth efficiency for high molar fractions of silane comes from the occurrence of a gaseous phase nucleation. The electronic properties of the resulting layers have been studied by Hall effect measurements. The values of electrons mobility (900 cm 2 Vs −1 for a low doped layer) compare well with those of other groups. Finally, Schottky diodes have been processed with good forward characteristics.

High temperature ohmic contacts to 3C-SiC grown on Si substrates by chemical vapor deposition

Abstract The properties of SiC have great potential for high temperature electronic device applications. For the realization of these devices the formation of stable (at elevated temperatures), low resistance ohmic contacts is required. For this purpose, multiple metallization schemes have been investigated on 3C-SiC grown on Si substrates by the chemical vapor deposition method. Both thick layers and thin multilayers of metals, deposited by electron beam evaporation, have been studied. Most of the metallizations exhibited ohmic behavior as-deposited even for relatively low doping levels due to the high concentration of defects in the SiC films. Annealing at temperatures up to 850 °C and ageing tests up to 550 °C were used to examine their thermal stability. The use of Al as contact overlayer instead of Au resulted in more stable contacts. The Cr/Ti/Pt/Mo/Al metal scheme produced the best results. On samples with doping (1–3) × 10 17 cm −3 an R c = 5.5 × 10 −6 Ω cm 2 was obtained while on samples with doping 3 × 10 18 cmu−3 an R c = 6 × 10 −7 Ωcm 2 before ageing and 7 × 10 −5 Ωcm 2 after 400 h at 550 °C was observed.

Comparison of the electrical and optical properties of 3C-SiC on SOI from different origin

Abstract We report on 3C-SiC laters deposited on separation by implanted oxygen (SIMOX) substrates obtained from two different origins. In both cases, using X-ray diffraction measurements, we evidenced a good relaxation of the residual strain inside the SiC layer. However, from X-ray transmission electron microscopy (XTEM) and infrared reflectivity measurements, we observed large cavities and Si islands located inside the buried oxide. Depending on the sample origin, they were in different amount. In spite of these structural defects we could evidence, from square resistance measurements, an improvement in the SiC layer insulation of approximately 100 °C when compared with SiC/Si. An upper limit of 640 K was even reached for the sample which exhibits the best silicon-on-insulator (SOI) characteristics.

TEM characterization of high Tc superconductive multilayered thin films

Abstract Superconductive multilayered thin films have been deposited by excimer laser ablation and d.c. magnetron sputtering. The laser deposited films were grown on (100) SrTiO 3 substrates and consisted of alternating layers of La 2− x Sr x CuO 4 (LSCO) and YBa 2 Cu 3 O 7−δ (YBCO) while the sputtered films, deposited on (100) MgO substrates, consist of a 3 nm MgO layer sandwiched in 100 nm YBCO layers. Cross-sectional transmission electron microscopy (TEM) specimens have been prepared so as to investigate the different interfaces and the local structure of the films. The results show that the laser deposited films are epitaxially grown with the c- axis normal to the surface. The interfaces are rather sharp but some roughness of the YBCO over LSCO interface, possibly related to the presence of shear defects in the LSCO layers, is evidenced. The observations of the sputtered films reveal the presence of some a- axis oriented YBCO grains and the partial crystallization of the amorphous deposited MgO layer. Some a- axis oriented grains are also observed in the laser deposited films but only in the upper layers. The different types of structural defects as well as the different interfaces, characterized by high resolution electron microscopy (HREM), will be reported.