L. Dupas

Evaluation of TSV and micro-bump probing for wide I/O testing

Practical silicon stacking requires pre-tested dies, but contact probing of TSV interconnects requires much higher density, lower probing forces, and lower cost per pin than conventional probe cards have achieved. This paper examines a cost-effective, lithographic-based MEMS probe card technology that is suitable for probing 40µm pitch arrays, and scalable to finer pitches. Initial mechanical and electrical results are presented, demonstrating the feasibility of probing large arrays at 1 gram-force per tip with very low pad damage, so as not to impair downstream bonding or other processing steps.

Process Technology Optimization Using An Integrated Process and Device Simulation Sequencing System

In this paper, we discuss a system for performing process optimization, and its application to the optimization of a 0.5μm CMOS process. The approach includes an initial Target-Oriented experimental design strategy, elimination of ineffective parameters, a second set of experiments to determine a set of approximating models for each response, detection of appropriate transformations of input factors which improve the accuracy of the models, and optimization with respect to a set of constraints.

The implementation of the power law model in silicon oxidation process simulation

The purpose of this work is to extend the power-law model1 to a semi-empirical oxidation model for process simulation. The proposed model benefits from a very simple model formulation, when compared to an existing model there are fewer parameter variables and simpler expressions of parameter dependence for a wide range of oxidation conditions while maintaining a very good overall fitting accuracy. The model covers dry oxidation for different pressures, temperatures, orientations, oxidation in a HC1/O2 ambient, doping enhanced oxidation phenomena, as well as wet oxidation for different pressure, orientation and temperature conditions. To develop the model, a strategy for parameter extraction,2 combined with optimal adaptation is proposed. This approach includes two steps. One is the determination of the parameter correlation matrix and the e-indifference range for each oxidation condition(e.g. temperature). The second step is the parameter adaptation within the ε-indifference range to obtain a simple parameter variation over a wide range of oxidation conditions. As a consequence of this work, the proposed model is a possible replacement for the oxidation model of SUPREM-33 in process simulation. The optimized parameter extraction strategy can be applied to a large class of modelling problems.

MOS technology for VLSI

Abstract The scaling laws for MOS transistors are reviewed and the optimum performance predicted for both n-channel and p-channel devices are discussed. The physical and technological limitations for MOS VLSI are then described and some important technological challenges such as the implementation of new isolation techniques are pointed out. The mobility degragation effect due to velocity saturation is explained and illustrated by experimental data. The various limitations to the maximum operating voltage of scaleg devices are discussed. Finally, some considerations about speed and power consumption of scaled technologies are made.

Transistor optimisation for a low cost, high performance 0.13 μm CMOS technology

Abstract This paper discusses the optimisation of a high performance, low cost 0.13 μm CMOS technology with a view on its further scaling to the 100 nm technology node. The focus is mainly on gate oxide (thickness and nitridation method), deep junction implants and annealing. It is shown that in order to take the full benefit of gate oxide thinning, low energy boron implants and spike rapid thermal anneal are mandatory for pMOS devices. The same route gives also promising results for nMOS transistors when gate predoping is used to reduce gate depletion.