Kristin De Meyer

Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance

Through-silicon via (TSV) constitutes a key component interconnecting adjacent dies vertically to form 3-D integrated circuits. In this letter, we propose a method to exploit the TSV C-V behavior in a p-silicon substrate to achieve minimum TSV capacitance during 3-D circuit operation. The nature of the TSV C-V characteristics depends both on TSV architecture and TSV manufacturing process, and both these factors should be optimized to obtain the minimum depletion capacitance in the desired operating voltage region. Measured C-V characteristics of the TSV demonstrate the effectiveness of the method.

Electrical TCAD Simulations of a Germanium pMOSFET Technology

A commercial technology computer-aided design device simulator was extended to allow electrical simulations of sub-100-nm germanium pMOSFETs. Parameters for generation/recombination mechanisms (Shockley-Read-Hall, trap-assisted tunneling, and band-to-band tunneling) and mobility models (impurity scattering and mobility reduction at high lateral and transversal field) are provided. The simulations were found to correspond well with the experimental I- V data on our Ge transistors at gate lengths down to 70 nm and various bias conditions. The effect of changes in halo dose and extension energies is discussed, illustrating that the set of models presented in this paper can prove useful to optimize and predict the performance of new Ge-based devices.

Write/erase cycling endurance of memory cells with SiO/sub 2//HfO/sub 2/ tunnel dielectric

The write/erase cycling endurance of low voltage floating-gate memory cells programmed and erased by tunneling through a SiO/sub 2//HfO/sub 2/ dual layer tunnel dielectric stack is investigated. The use of fixed single pulse program and erase conditions leads to fast shifting (after /spl sim/1000 cycles) of the threshold voltage window, so that only a limited number of write/erase cycles can be achieved. Increasing the write and erase duration quickly leads to an excessive erase time so that a different erase method has to be used. Improvement of the erase behavior and cycling endurance has been obtained by a combination of two methods. Inclusion of soft write pulses between the erase pulses reduces the amount of charge trapped in the tunnel dielectric and therefore limits the increase in erase time. Also, the erase voltage can progressively be raised in order to further limit the erase time, leading to an endurance of 10 000 cycles on the considered cells. When combining the SiO/sub 2//HfO/sub 2/ stack with channel hot electron injection so that tunneling is only required in one direction, 100 000 write/erase cycles are demonstrated with minimal change of the memory window.

Vertical GAAFETs for the Ultimate CMOS Scaling

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules.

Transient effects in PD SOI MOSFETs and potential DRAM applications

Abstract The transients in partially depleted (PD) silicon on insulator (SOI) MOSFETs produced with 0.25 and 0.13 μm technologies are studied. The exponential dependence of the switch-on transient time on the reciprocal drain voltage for both P- and N-channel devices is explained by the predominance of the impact ionisation mechanism. A pulse method to measure output I – V curves using short gate pulses has been applied to study self-heating and transient effects in 0.13 μm SOI N-MOSFETs. It is shown that under normal operating conditions the difference between DC and pulsed I – V curves of PD SOI MOSFET is attributed mainly to the floating body effect and not to self-heating. We demonstrate also that it is possible to use the body charging of PD SOI devices to store information. Based on this effect, an original 1T-DRAM cell concept is proposed (DRAM: dynamic random access memory). This cell is at least two times smaller in area than the conventional 1T/1C DRAM cell and does not require the integration of a storage capacitor. This concept allows the manufacture of low cost DRAMs and embedded DRAMs for 100 and sub-100 nm generations.

High FET Performance for a Future CMOS

In Germanium-based metal-oxide-semiconductor field-effect transistors, a high-quality interfacial layer prior to high-¿ deposition is required to achieve low interface state densities and prevent Fermi level pinning. In this letter, the physical and electrical properties of a Ge/GeO2/Al2O3 gate stack are investigated. The GeO2 interlayer grown by radical oxidation and the formation of a germanate (GeAlOX) layer at the interface provide a stable high-quality passivation of the Ge channel. High carrier mobilities (235 cm2/V·s for electrons and 265 cm2/V·s for holes) are demonstrated for a relatively low 3.7-nm equivalent oxide thickness (EOT), enabling the realization of a high-performance CMOS technology with potential EOT scaling.

\hbox{GeO}_{2}

Abstract A new process flow is proposed (C.J.R.P. Augusto, U.S. Provisional Patent Appl. No. 60/008703, 1995) for the fabrication of silicon-based MOD-MOSFETs, with or without SiGe relaxed buffer layers. In this process flow, a single, blanket, epitaxial step is used to make all regions of the complementary devices. No ion implantation is required, thereby lifting thermal budget constraints on the metastability of the epitaxial films. Because this process flow can be used to produce recessed-gate MOSFETs, this architecture can be scaled to the 0.1 μm region, preserving very low leakage currents, independent of the drain bias. Moreover, the number of processing steps needed to fabricate these devices is greatly reduced.

-Based Technology

Abstract In this paper, we present a model for the tunneling currents through multi-layer stacks based on the independent electron approximation and using an Airy functions based transfer matrix formalism. The transmission coefficient of a tunneling electron is exactly calculated using a simple compact quasi-analytical formula. Comparison with the traditional WKB models reveals differences for particular stack structures. This model is applied to the analysis of multi-layer tunnel dielectrics that aim at replacing the conventional tunnel oxide in non-volatile memory devices. Analysis of the tunneling current for dual-layer stacks shows possibilities for higher speed and/or lower voltage programming, which can be achieved with high- k materials considered for SiO 2 replacement as gate dielectric.

Proposal for a new process flow for the fabrication of silicon-based complementary MOD-MOSFETs without ion implantation

We develop a model for the tunnel field-effect transistor (TFET) based on the Wentzel-Kramer-Brillouin approximation which improves over existing semi-classical models employing generation rates. We hereby introduce the concept of a characteristic tunneling length in direct semiconductors. Based on the model, we show that a limited density of states results in an optimal doping concentration as well as an optimal material’s band gap to obtain the highest TFET on-current at a given supply voltage. The observed optimal-doping trend is confirmed by 2-dimensional quantum-mechanical simulations for silicon and germanium.

A model for tunneling current in multi-layer tunnel dielectrics

Group IV based tunnel field-effect transistors generally show lower on-current than III-V based devices because of the weaker phonon-assisted tunneling transitions in the group IV indirect bandgap materials. Direct tunneling in Ge, however, can be enhanced by strain engineering. In this work, we use a 30-band k · p method to calculate the band structure of biaxial tensile strained Ge and then extract the bandgaps and effective masses at Γ and L symmetry points in k-space, from which the parameters for the direct and indirect band-to-band tunneling (BTBT) models are determined. While transitions from the heavy and light hole valence bands to the conduction band edge at the L point are always bridged by phonon scattering, we highlight a new finding that only the light-hole-like valence band is strongly coupling to the conduction band at the Γ point even in the presence of strain based on the 30-band k · p analysis. By utilizing a Technology Computer Aided Design simulator equipped with the calculated band-t...