L.-J. Huang

A “smarter-cut” approach to low temperature silicon layer transfer

Silicon wafers were first implanted at room temperature by B+ with 5.0×1012 to 5.0×1015 ions/ cm2 at 180 keV, and subsequently implanted by H2+ with 5.0×1016 ions/cm2 at an energy which locates the H-peak concentration in the silicon wafers at the same position as that of the implanted boron peak. Compared to the H-only implanted samples, the temperature for a B+H coimplanted silicon layer to split from its substrate after wafer bonding during a heat treatment for a given time is reduced significantly. Further reduction of the splitting temperature is accomplished by appropriate prebonding annealing of the B+H coimplanted wafers. Combination of these two effects allows the transfer of a silicon layer from a silicon wafer onto a severely thermally mismatched substrate such as quartz at a temperature as low as 200 °C.

FUNDAMENTAL ISSUES IN WAFER BONDING

Semiconductor wafer bonding has increasingly become a technology of choice for materials integration in microelectronics, optoelectronics, and microelectromechanical systems. The present overview concentrates on some basic issues associated with wafer bonding such as the reactions at the bonding interface during hydrophobic and hydrophilic wafer bonding, as well as during ultrahigh vacuum bonding. Mechanisms of hydrogen-implantation induced layer splitting (“smart-cut” and “smarter-cut” approaches) are also considered. Finally, recent developments in the area of so-called “compliant universal substrates” based on twist wafer bonding are discussed.

ONSET OF BLISTERING IN HYDROGEN-IMPLANTED SILICON

The onset of surface blistering in hydrogen-implanted single crystalline silicon was studied. A combination of atomic force microscopy and optical measurements shows that hydrogen-containing platelets grow laterally below silicon surface until they suddenly pop up as surface blisters due to the internal hydrogen pressure after a critical size has been reached. Experimentally and theoretically, the critical size of the onset blisters was found to increase with increasing implantation depth or top layer thickness.

IOS-a new type of materials combination for system-on-a chip preparation

IOS (insulator-on-semiconductor) has emerged as a new type of materials combination for system-on-a chip preparation. For high frequency mobile communication systems, a thin layer of piezoelectric or ferroelectric oxide crystal such as quartz, LiTaO/sub 3/ or LiNbO/sub 3/ on Si is required for high Q-factor and low temperature coefficient SAW filters, surface resonators and oscillators. Combining these materials with Si can lead to the integration of electronic and acoustic devices on the same chip. Voltage-controlled and temperature-compensated high Q-factor crystal oscillators and resonators can thus be realized. The integration of high performance GaAs photodetectors with LiNbO/sub 3/ waveguides makes integrated optical circuits possible. By preparing a thin layer of single crystalline transition metal oxides such as magnetic garnets on Si or on III-V semiconductors, stabilized laser diodes can be realized due to the availability of on-chip thin film optical isolators and circulators. Layer transfer by wafer bonding and H-induced layer splitting provides a manufacturable technology for IOS preparation. In this study, we report feasibility study results for IOS preparation with an insulator layer of many single crystalline insulators such as c-sapphire, LaAlO/sub 2/, PLZT and LiNbO/sub 3/. We have demonstrated that surface blistering and layer splitting of these materials is possible if H implantation is performed at wafer temperatures within the specific temperature range for each material.

Low dose layer splitting for SOI preparation

Summary form only given. Semiconductor-on-insulator (SOI) substrates are in increasing demand for many applications including low voltage, low power, RF/microwave wireless mobile computer and communication systems. High quality Si, SiC and GaAs on insulator materials have been realized by wafer bonding and H-implanted layer splitting (Jalaguier et al. 1998). Typically, a high hydrogen dose in the 5/spl times/10/sup 16/ to 1/spl times/10/sup 17/ H ions/cm/sup 2/ range is used for implantation to achieve layer splitting. For mass production of SOI materials, the fabrication cost is one of the main challenges. A reduction of hydrogen dose is essential not only for cost-effectiveness but also for a lower defect density in the split layers. We have found that implantation of a small dose of B prior to H implantation, with the two ion profile peaks aligned, can significantly lower the blistering temperature. At a fixed splitting temperature, it implies a reduction of the required H dose for layer splitting. The B+H co-implant method has been found to work not only for Si but also for SiC, Ge and GaAs.