Nikhil Vishwanath Kelkar

Lead-Free and PbSn Bump Electromigration Testing

As the electronics industry continues to push for miniaturization, several reliability factors become vital issues. The demand for a high population of smaller and smaller solder bumps, while also increasing the current, have resulted in a significant increase in the current density. As outlined in the International Technology of Roadmap for Semiconductors (ITRS), this trend makes electromigration the limiting factor in high density packages. The heightened current density and correspondingly elevated operating temperatures are a critical issue in reliability since these factors facilitate the effects of electromigration. Therefore, as bump sizes continue to decrease, the study of electromigration reliability becomes crucial in order to understand and possibly prevent the causes of failure. A systematic study of electromigration in eutectic SnPb and Pb-free solder bumps was conducted in order to characterize the reliability of the Micro SMD package family. The testing includes both eutectic 63Sn-37Pb and 95.5Sn4.0Ag-0.5Cu solder bumps on an Al/Ni(V)/Cu under-bump-metallization. Mean-time-to-failure results are compared to Black’s Equation and cross-sections of the solder bumps are shown to analyze the mechanisms that led to failure.Copyright

Numerical and experimental analysis of large passivation opening for solder joint reliability improvement of micro SMD packages

Abstract In this paper, using a recently developed solder fatigue model for wafer level-chip scale package (WL-CSP), we investigated the improvement on solder joint reliability for a 8-bump micro SMD package by enlarging the passivation layer opening at the solder–die interface. The motivation to enlarge the passivation opening is to reduce the severity of the stress concentration caused by the original design, and also to increase the contact area between the solder bump and aluminum bump pad. It was confirmed in the thermal shock test that with the new design, package fatigue life improved by more than 70%. To numerically predict this improvement represents a unique challenge to the modeling. This is because in order to capture the slightest geometrical difference on the order of a few microns between the two designs, the multiple-layer solder-die interface needs to be modeled using extremely fine mesh, while the overall dimensions of the package and the test board are on the order of millimeters. To bridge this tremendous gap in geometry, a single finite element model that incorporates all necessary geometrical details is deemed computationally prohibitive and impractical. In this paper, we applied a global–local modeling scheme that was also suggested by others [1] , [2] , [3] . The global model contains the complete package with much simplified solder–die interface whereas the local model includes only one solder joint, but with detailed solder–die interface. Unlike most global–local models proposed by others, we included time-independent plasticity and temperature-dependent materials in the global model. This greatly improved model correlation accuracy with only moderate increase in run time. Energy-based solder fatigue model was used to correlate the inelastic strain energy with the package fatigue life. In an earlier study [4] , we have found that Darveaux’s equations tended to be conservative when applied to the micro SMD, and hence new correlations based on curve-fitting the test data were derived. In this paper, we used the newly derived equation and achieved less than 20% error in N50 life for both designs, which is on par with Darveaux’s equations when used for BGAs. The analysis also revealed two factors that may account for the life improvement. First, a slight decrease in inelastic energy dissipation after enlarging the passivation opening. Second, the shift of the crack initiation location which leads to longer crack growth length for the new design. The second factor was also independently confirmed by the failure analysis.

Solder joint reliability model vath modified Darveaux's equations for the micro smd wafer level-chip scale package family

Historically, energy-based solder fatigue lie models have been used primarily for PBGA or similar package configurations. In this paper, we extend the energy-based method to newly emerged Wafer Level, Chip Scale Package (WL-CSP). National Semiconductor’s micro SMD package family was chosen as the test vehicle. Among all energybased methods, Darveaux’s model is arguably the most popular one due to its well-documented good correlation with the actual tests. To maintain consistency in results, Darveaux suggested that the solder joint be meshed such that the element size in its height direction has fixed value. However, we found in our study that Darveaux’s model faired poorly in capturing the package fatigue life, even though the mesh size issue was carefully addressed. In view of the drastic difference in solder ball size between WL-CSP and PBGA, on which Darveaux’s model is based, we argue that in addition to the element size in the solder height direction, the f~te element calculation of inelastic dissipation may also depend on other meshing parameters, which may vary depending on the specific geometry of the solder bump. Consequently, we proposed a revised empirical equation to calculate the package fatigue life for micro SMD. The new equation is derived from correlating the simulation results with the test data. We also demonstrated that the new equation was capable of achieving a similar accuracy level as compared with Darveaux’s model for PBGA packages. The study also provided for the first time a good parametric model scalable to larger micro Sh4D VO count. In addition, the impact of different modeling schemes was also evaluated in terms of their accuracy and eficiency.

MicroSMD-a wafer level chip scale package

This paper outlines National Semiconductors concept of wafer level chip scale package-also known as microSMD. This new packaging technology has been demonstrated using an 8 I/O package with 0.5 mm bump pitch, and is ideally tailored for low pin count analog and wireless devices. Product extensions to higher pin count (up to 48) are under various stages of qualification. The package construction, process flow, and package reliability are described, together with board level assembly processes and interconnect reliability.

A manufacturing perspective of wafer level CSP

The micro SMD package, a wafer level Chip Scale Package (CSP), was successfully introduced by National Semiconductor about two years ago for portable wireless applications where weight, thin form factor, and board space savings are as critical as increased functionality. The package provides a matrix interconnect layout at 0.5 mm pitch, does not require underfill, and leverages standard surface mount assembly techniques. This paper will evaluate the pros and cons of packaging this wafer level CSP against a conventional leaded package and a traditional CSP.

A parametric solder joint reliability model for wafer level-chip scale package

The micro-SMD is a Wafer Level-Chip-Scale Package (WL-CSP) designed to have external dimensions equal to that of the silicon device. This new package type extends flip-chip packaging technology to standard surface mount technology. The package has been successfully targeted for low pin count (less than 30), high volume applications such as cellular phones, hand-held PDAs, etc. Since the WL-CSP is typically used without underfill, solder joint reliability is of prime concern. A good understanding of the device failure mechanism when assembled on different board configurations is critical to the development of an accurate predictive model of solder fatigue. This paper presents results of a joint effort to develop a parametric predictive model of the solder joint reliability of the micro-SMD subjected to thermo-mechanical stresses. An 18 I/O micro-SMD was used as the primary test vehicle for the thermal cycling and thermal shock tests performed with different ramp/hold profiles. The parametric model developed can be extended to different pin count and die size of WL-CSPs with eutectic solder.

Lead-free wafer level-chip scale package: assembly and reliability

This paper discusses the reliability testing results of a lead-free version of the micro SMD, National Semiconductors Wafer Level-Chip Scale Package (WL-CSP). The micro SMD, a true wafer scale package has proven to be highly adaptable in the conventional assembly process, requiring no special considerations during the surface mount assembly operation. The current micro SMD utilizes standard Sn/Pb solder bumps as the interconnect medium. Based on evaluations of the various options available for the lead-free solder, micro SMD devices bumped with Sn/Ag/Cu solder were tested during this evaluation. There are two bump sizes currently available for the micro SMD package, a 170-micron bump diameter and a 300-micron bump diameter. This paper addresses the impact of board assembly conditions, package solder type, package bump size, and thermal cycling profiles on the reliability of the lead-free WL-CSPs. This paper will address the initial evaluations on the 170-micron bumped micro SMD packages. Results of this work are used to determine viable combinations of lead-free and eutectic solder. The lead-free version of the micro SMD is in synch with the next packaging evolutionary stage toward a lead-free assembly process.