Lars Böttcher

Large area embedding for heterogeneous system integration

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing with potential for low cost applications. Wafer level embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the use of compression and transfer molding techniques for multi chip embedding in combination with large area and low cost redistribution technology from printed circuit board manufacturing as adapted for Chip-in-Polymer applications. The work presented is part of the German governmental funded project SmartSense. Embedding by transfer molding is a well known process for component embedding that is widely used for high reliable microelectronics encapsulation. However, due to material flow restrictions transfer molding does not allow large area encapsulation, but offers a cost effective technology for embedding on a medium size scale as known e.g. from MAP (molded array packaging) molding (typically with sizes up to 60 × 60 mm2). In contrast, compression molding is a relatively new technology that has been especially developed for large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically up to 8” or even up to 12”. Wiring of these embedded components is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components - no matter which shape the embedded components areas are: a compression molded wafer, larger rectangular areas or smaller transfer molded systems (MAP). Typical process flow for RCC redistribution is lamination of RCC, via drilling to die pads by laser, galvanic Cu via filling, conductor line and pad formation by Cu etching, soldermask and solderable surface finish application - all of them standard PCB processes. The feasibility of the technology is demonstrated by the fabrication of a Land Grid Array (LGA) type package with two embedded dies. First step is a high precision die placement on an intermediate carrier. For embedding, both compression molding and transfer molding are used and directly compared with regards to material properties, processing, resulting die shift and warpage after molding. Reliability testing including MSL testing, temperature cycling, and humidity storage has been performed with LGA packages manufactured using the different technologies. The reliability potential and failure modes are intensively discussed and backed by destructive and non destructive failure analysis. Finally, an outlook for the integration of through mold vias into RCC redistribution process flow is given showing also the potential for package stacking.

Highly integrated flexible electronic Circuits and Modules

Within the electronic circuit board industry flexible circuit still cover a small the market share, however, with the fastest growth rate. The technology is increasingly used in automotives and aerospace, in handheld mobile appliances and many medical devices like pace makers or hearing aids [1,2]. Over past years a European consortium of research institutes and industry has explored the future technological potential of flexible printed circuits in the framework of the project SHIFT. One aspect was to investigate the frontiers of flexible circuit fabrication with respect to minimum feasible line width and pitch using different manufacturing methods. Still further beyond today mainstream flex fabrication technologies were the developments to integrate active and passive components into the buildup layers of flex circuits. In this way extremely high integration of electronic systems and highest functional densities can potentially be realized. Techniques and results of these developments will be presented in this paper. Embedded components in order to comply with the thin buildups of flexible circuits should be very thin as well. To this aim components were be mechanically thinned to 20 ptm. A dicing by grinding technique was applied using etched separation grooves on the wafer. Two technologies for embedding of ultra thin components were developed. The first one is thin flip chip assembly on inner layers of the flex and embedding by subsequent lamination of build up layers. The gap between chip and substrate was in the order of a few microns using either low profile solder or anisotropic adhesive.

Design of 77 GHz Interconnects for Buried SiGe MMICs Using Novel System-in-Package Technology

This paper describes the design, simulation and measurement of interconnects of buried active 77 GHz chips to a high frequency substrate using microvia technology. The embedding technology proposed offers great opportunities for a very broad range of frequencies and applications as well as a large potential for cost reduction.

Embedding technologies for an automotive radar system

Radar sensors are already employed in production model vehicles e.g. for adaptive cruise control (ACC) systems. Further development of driver assistance systems has also led to the use of radar sensors in active safety systems (active brake assistance, collision warning, emergency braking, etc). However, the costs of manufacturing such radar-based systems, capable of gathering reliable information from surroundings, for vehicles across the market spectrum or for compact executive cars are still too high. Thus, despite the improved reliability characteristics, detection properties and safety required for these sensors, the aim is to manufacture such systems more cost-effectively. The German national “KRAFAS (Cost-optimized Radar Sensor for Active Driver Assistance Systems)” project is aiming at integrating 77 GHz components (esp. SiGe MMICs) into a printed circuit board, combining driver and 77 GHz RF circuitry and integrating antenna elements. This will significantly reduce current costs of the 77 GHz RF module by 20–30%. A sketch of such a module with an adapted cylindrical radar lens is depicted in Figure 1. In this paper, design, simulation, technological development, demonstrator realization and subsequent measurement of interconnects of embedded active 77 GHz chips to a high frequency substrate using microvia technology is described. The used molded embedding technology offers great opportunities for a very broad range of frequencies and applications as well as large potential for cost reduction.

Microtechnology For Realization Of Dielectrophoresis Enhanced Microwells For Biomedical Applications

Microtechnologies are widely used in many applications as e.g. for the automotive or telecommunication industry. But it could be also a versatile tool for biological and biomedical applications. Microwells have been established long in this application field but remained without any additional functionality up to now. Merging new fabrication techniques and handling concepts with microelectronics enables the realization of intelligent microwells suitable for future applications e.g. improved cancer treatment. For the implementation of a dielectrophoresis enhanced microwell device a technology based on standard PCB technology has been developed. But as materials from PCB technology are not biocompatible new materials have to be selected, tested and processes adapted to these new packaging materials. With promising preselected materials for an enhanced microwell device biocompatibility tests have been carried out. As base conducting metal layer aluminum has been selected. Different dielectric materials were evaluated with focus on their processability. Goal of this preselection study was to find materials, which allow a fine structuring and realization of thin layers for the required application geometries. Thin aluminum foils are structured by laser micro machining and laminated successively to obtain minimum registration tolerances of the respective layers. The microwells are also laser machined into the laminate, allowing capturing and handling individual cells within a dielectrophoretic cage realized by the structured aluminum as well as providing access holes for the layer-to-layer interconnection. Furthermore, surface treatments with e.g. thiols and fluorinated acrylates on different materials were inspected by surface tension and wetting analysis to allow designing the hydrophilic/hydrophobic microfluidic networks required for the microwell device. First demonstrators are presenting the developed technologies and structures realized. In summary this paper describes the material selection for a biocompatible microwell device, the development of the individual process steps and results on the microstructuring as well as on biocompatibility of the materials are given.

Interconnects for Buried W-Band MMICs Using Novel System-in-Package Technology

A novel system-in-package technology has been developed which enables to bury active 77 GHz chips inside a printed circuit board (PCB). The chips are connected to an RF substrate on top of the PCB using microvias. To evaluate the performance of these interconnects, silicon daisy chain chips with coplanar lines are buried inside a PCB. Simulation and measurement data are compared. The embedding technology proposed offers great opportunities for a very broad range of frequencies and applications as well as a large potential for cost reduction.

Biocompatible Lab-On-Substrate technology platform

Multiwell plates in combination with optical inspection equipment are standard tools for biological and biomedical applications e.g. cell-to-cell interaction studies for cancer treatment. Microtechnology based multiwell plates have the potential to monitor physiological cellular interactions at single cell level with a high throughput e.g. for immunotherapy of cancer or targeted drug delivery, where each patient would receive drugs that are known to be useful for his/her specific situation.

Trends in Fan-out wafer and panel level packaging

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. Besides developments to higher and heterogeneous integration the movement to larger formats and panel level packaging to lower cost is noticeable.