Laura Gobbi

Voltage Gain Analysis of Integrated Fibonacci-Like Charge Pumps for Low Power Applications

This paper presents an analysis of the achievable voltage gain in integrated Fibonacci-like charge pumps. The analysis is carried out by using a mathematical model based on a matrix description of the network which takes parasitic capacitances into account. The impact of top- and bottom-plate parasitics over the voltage gain is discussed and the analytical expression of the voltage gain as a function of parasitic capacitances is obtained. The derived set of equations is validated by means of circuit level simulations.

A discussion on exponential-gain charge pump

This paper presents a discussion about the performance achievable by an exponential-gain charge pump (i.e., by a charge pump featuring a voltage gain which increases exponentially with the number of stages). This charge pump topology is analyzed in terms of both voltage gain and equivalent output resistance. An analytical expression of these two parameters is provided, which allows performance comparison with other charge pump topologies. The expression of the output voltage rise time is also derived.

Impact of parasitic elements on CMOS charge pumps: a numerical analysis

In this work, a numerical method for the evaluation of the topological properties of integrated CMOS charge pumps is presented. The analysis is based on a matrix description of the charge pump, which is used to define the network during the different operating phases. The proposed method allows the contribution of the non idealities of the structure (in particular, the parasitic elements) to be accurately taken into account. This way, a complete description of the charge pump behavior can be obtained. Furthermore, since the voltage at any internal node of the structure can be evaluated, the overall power efficiency can also be calculated, thus allowing a comparison between different topologies. The proposed formulation has been automated by computer implementation and easily adapted to analyze several charge pump structures with different number of capacitors and switches. A comparison with circuit simulator results confirms the effectiveness of the proposed method

A theoretical discussion on performance limits of CMOS charge pumps

This paper presents a study of the theoretical performance of CMOS integrated charge pumps (CPs). The discussion is based on a behavioural model of the CP and a mathematical manipulation of power efficiency definition. The CP theoretical limit is found in terms of both power efficiency and maximum driving capability. The basic idea is to analyze the performance of any CP only considering the voltage gain, the output resistance, the number of capacitors and parasitic capacitances. Experimental results are presented to validate the theoretical analysis.

Theoretical and experimental analysis of Dickson charge pump output resistance

This paper presents an analytical and experimental evaluation of the output resistance of Dickson charge pumps. This work is conceived to obtain an accurate estimation of the parameters affecting the charge pump output resistance, with particular attention to the capacitance connected to the output node of the circuit. The aim is to evaluate the impact of this element over charge pump performance in terms of output resistance and, hence, of power efficiency, output voltage and driving capability. The presented analysis gives a suitable criterion for properly sizing the charge pump capacitors, which allows the charge pump performance to be optimized. Simulated and experimental results are provided so as to validate the proposed model

Design of Maximum-Efficiency Integrated Voltage Doubler

In this paper, an algorithm and the analytical expressions to be used for the design of maximum-efficiency integrated charge pumps based on the voltage doubler architecture are presented. Starting from basic considerations on charge transfer, the proposed methodology allows adequate choice of the stage number and of the size of all charge pump elements, namely, capacitors, transfer switches, and phase drivers. The whole design flow ensures the target output voltage and output current values to be achieved taking the parasitic elements (capacitances and switch on-resistances) into account. The proposed design strategy was implemented in C#reg environment, thus allowing an automated CP design.

A Versatile and Compact USB System for Electrical and Thermal Characterization of Non-Volatile Memories

This paper presents a multipurpose, versatile and portable test equipment suitable for non-volatile memories performance evaluation. The system is based on a reconfigurable testing board which can be controlled and programmed by a personal computer through the USB interface. The proposed solution allows the device under test to be supplied with the required bias and control signals and to be measured by means of analog and digital acquisition channels. The system was conceived for the testing of program and erase algorithm to be used for non-volatile flash memories as well as for the temperature characterization of analog integrated circuits. In fact, the availability of a large number of signals (each one having independent and programmable voltage range) make it possible to easily implement flexible control routines needed for the testing of integrated devices which, in our case, typically include only a memory array. A smart graphic interface and the use of well known programming languages simplify the test flow and the processing of the measured data thus allowing fast and efficient device characterization

A theoretical charge transfer scheme for efficiency optimization of integrated charge pumps

A scheme which provides optimized charge transfer for integrated charge pumps is presented. The pump capacitors in the intermediate stages of the pump are split into k smaller capacitors C/k. Higher charge transfer efficiency is achieved by sequentially transferring charge packets from a capacitor C to each of the cascaded k capacitors C/k and, then, by sequentially connecting each of these k capacitors to a cascaded stage capacitor C. Mathematical analysis and circuit simulations show that a charge pump based on the proposed method features reduced output resistance with respect to conventional solutions which results in higher power efficiency, thus making the proposed scheme very well suited to low-power devices.

High-Efficiency CMOS Charge Pump

A charge pump topology with enhanced driving capability for very low voltage applications is presented. The proposed scheme is able to operate with a supply voltage as low as 900 mV and ensures high voltage gain, high driving capability, and high power efficiency over the whole current range. A suitable boosting circuit allows adequately low on-resistance of transfer devices while still limiting the impact of parasitic capacitances. Simulation results show the effectiveness of the proposed approach.