Laurent Paumier

A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes

A CODEC fully compliant to DVB-S2 broadcast standards is implemented in both 0.13 /spl mu/m 8M and 90nm 7M low-leakage CMOS technologies. The system includes encoders and decoders for both LDPC codes and serially concatenated BCH codes. This CODEC outperforms the DVB-S2 error performance requirements by up to 0.1dB. The 0.13 /spl mu/m design occupies 49.6mm/sup 2/ and operates at 200MHz, while the 90nm design occupies 15.8mm/sup 2/ and operates at 300MHz.

A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling Satellite-Transmission Portable Devices

The design of a full broadcast + interactive services compliant 2nd generation satellite digital video broadcast (DVB-S2) codec is presented.

A generic 350 Mb/s turbo-codec based on a 16-states SISO decoder

The implementation of a 350 Mb/s 16-state SISO turbo decoder and its corresponding coder are described. It performs within 1.8 dB of Shannons limit in terms of error correction. Implemented in 0.13 /spl mu/m low-leakage technology, this codec occupies 10 mm/sup 2/ and is designed using a Matlab-to-RTL design flow.

A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)

A DVB-S2 compliant codec is implemented in both 130nm-8M and 90nm-7M low-leakage CMOS technologies. The system includes encoders and decoders for both low-density parity check (LDPC) codes and serially concatenated BCH codes. All requirements of the DVB-S2 standard are supported including code rates between 1/4 and 9/10, block sizes of either 16,200 bits or 64,800 bits, and four digital modulation options. The 130nm core design occupies 49.6mm2 and operates at 200MHz, while the 90nm core design occupies 15.8mm2 and operates at 300MHz.