Vincent Heinrich

A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling Satellite-Transmission Portable Devices

The design of a full broadcast + interactive services compliant 2nd generation satellite digital video broadcast (DVB-S2) codec is presented.

A self-powered IPv6 bidirectional wireless sensor & actuator network for indoor conditions

This paper demonstrates an IPv6 self-powered bidirectional wireless network system solution, compatible with indoor conditions, based on a IEEE 802.15.4/802.14.4e 2.4GHz radio (5.4mA Rx / 7.3mA Tx) and a 130nA quiescent current Power Management Unit (PMU). Other key elements are a 32bits Cortex M3 microcontroller and MEMs for sensors. This chipset enables self-powered sensors and actuators as well as over-the-air programing. It is able to sustain a working/home environment (100 lux CLF light during 6 hours a day), able to harvest as low as 1uW energy, and keep operating in the dark during more than 2 months.

Efficient performance evaluation of Forward Error Correcting codes

Standard Monte Carlo (SMC) simulation is employed to evaluate the performance of forward error correcting (FEC) codes. This performance is in terms of the probability of error during the transmission of information through digital communication systems. The time taken by SMC simulation to estimate the FER increases exponentially with the increase in signal-to-noise ratio (SNR). We hereby present an improved version of fast flat histogram (FFH) method, an adaptive importance sampling (AIS) technique inspired by algorithms existing in statistical physics. We show that the improved FFH method employing Wang Landau algorithm based on a Markov chain Monte Carlo (MCMC) sampler reduces the simulation time of the performance evaluation of complex FEC codes having different code rates.

Fast Simulation for the Performance Evaluation of LDPC Codes using Fast Flat Histogram Method

The quality of transmission in digital communication systems is usually measured by frame error rate (FER). The time taken by standard Monte Carlo (MC) simulation to estimate the FER increases exponentially with the increase in signal-to-noise ratio (SNR). In this correspondence, we present an Adaptive Importance Sampling (AIS) technique inspired by statistical physics called fast flat histogram (FFH) method to evaluate the performance of LDPC codes with a reduced simulation time. The FFH method employs Wang Landau algorithm based on a Markov Chain Monte Carlo (MCMC) sampler and we managed to decrease the simulation time by a factor of 13 to 173 for LDPC codes with block lengths up to 2640 bits.

Non-binary split LDPC codes defined over finite groups

In this paper, we propose a practically implementable decoding algorithm for split LDPC codes with parity constraints defined over finite groups. The proposed decoding algorithm generalizes the orders of the variable and check nodes such that it may have messages of different order at the various nodes. This gives us a further degree of freedom in terms of better code construction. Using the binary image of the parity check matrix, we define the function node which maps lower order messages to higher order and vice-versa. In order to have a reduced compexity decoder which is practically implementable, we use the truncated messages concept at the check nodes and evaluate its performance. We show improved performance in the error floor region as compared to other non-split low complexity decoding algorithms.

A 40nm CMOS, 1.27nJ, 330mV, 600kHz, Bose Chaudhuri Hocquenghem 252 bits frame decoder

Following the will to answer to the energy constrained applications requirements, an Ultra-Low Voltage (ULV) 40nm Bose-Chaudhuri-Hocquenghem (BCH) error-correcting circuit is presented. Mapped on a ULV specific standard cells library, the circuit was designed following standard industrial implementation and verification flows. The BCH circuit runs at 0.330V, 600kHz frequency and needs 1.27nJ to decode a 252bits frame. With 14% of extra power compared to typical process, applying forward bias enables to compensate temperature and skewed process effects, regaining 150mV minimum operating voltage.

Voltage scaling and body biasing methodology for high performance hardwired LDPC

This paper aims at introducing a safe voltage scaling and body biasing methodology for Low-Density Parity Check (LDPC) hard-wired IP. The proposed methodology allows an efficient post-silicon tuning of the LDPC, and the performances can be adapted to High Speed mode, or Low Operating Power mode, or Low Standby Power mode requirements. Concrete 45nm silicon results are introduced in this paper to demonstrate the added value of the methodology. More precisely, it is shown that running the High Performance mode leads to +24% on circuit maximum operating frequency. And the Low Standby Power mode results on x0.73 leakage minimization. The proposed adaptive LDPC encoder/decoder can remove some barriers to the adoption of long LDPC codes on portable devices.

Improved decoding Architecture for non-binary split LDPC codes defined over finite groups

In this paper, we propose an improvement of the previously proposed decoder for split LDPC codes defined over finite groups. The output of the check nodes is adjusted such that it bears better resemblance to that of more complex and efficient algorithms. There is a significant improvement in the decoding performance with almost no oeffect on the decoding complexity. The hardware architecture for the proposed decoder is explained in detail and we show with Monte-Carlo simulations that the performance is indeed improved.

An efficient pseudo-codeword search algorithm for Belief Propagation decoding of LDPC codes

We introduce the use of Fast Flat Histogram (FFH) method employing Wang Landau Algorithm in an adaptive noise sampling framework using Random Walk to find out the pseudo-codewords and consequently the pseudo-weights for the Belief Propagation (BP) decoding of LDPC codes over an Additive White Gaussian Noise (AWGN) channel. The FFH method enables us to tease out pseudo-codewords at very high Signal-to-Noise Ratios (SNRs) exploring the error floor region of a wide range of codes varying in length and structure. We present the pseudo-weight (effective distance) spectra for these codes and analyze their respective behavior.