Lauri Knuuttila

Low Temperature Growth GaAs on Ge

In this work, low temperature growth of GaAs epitaxial layers on Ge substrates by metalorganic vapor phase epitaxy has been studied. The experiments show that a growth temperature of 530°C and a V/III ratio of 3.5 result in smooth GaAs surfaces. Atomic force micrographs do not show any anti-phase boundaries on the surface of GaAs grown on a misoriented substrate. X-ray diffraction curves show that the layer tilt is reduced as the growth temperature is lowered. Synchrotron X-ray topography reveals very low threading dislocation densities of 300 cm-2 for the GaAs epitaxial layers. Additionally, no misfit dislocations are observed. If a single layer is deposited at low temperature, secondary ion mass spectrometry shows a considerably reduced arsenic diffusion into Ge. When an additional layer is deposited at higher temperature on top of the initial low temperature layer, a substantial increase for the deep concentration-dependent arsenic diffusion is found.

Evaluation of mechanical stresses in silicon substrates due to lead-tin solder bumps via synchrotron X-ray topography and finite element modeling

Solder-based flip-chip packaging has prompted interest in integrated circuit (IC) packaging applications due to its many advantages in terms of cost, package size, electrical performance, input/output density, etc. The ball grid array (BGA) is one of the most common flip-chip packaging techniques used for microprocessor applications. However, mechanical stresses induced by the flip-chip process can impact adversely on the reliability of products. Synchrotron X-ray topography (SXRT), a non-destructive technique, has been employed to investigate the spatial extent of strain fields imposed on the underlying silicon substrate for Intel® Pentium® III microprocessors due to the lead-tin solder bump process for BGA packaging. Large area and section back-reflection SXRT images were taken before and after a simulation of the reflow process at 350 °C in atmosphere. The presence of induced strain fields in the Si substrate due to the overlying bump structures has been observed via the extinction contrast effect in these X-ray topographs. In addition, orientational contrast effects have also been found after the reflow process due to the severe stresses in the underlying silicon beneath the lead bumps. The estimated magnitudes of stress, |σ|, imposed on the underlying silicon were calculated to be of the order of 100 MPa. The spatial strains in the underlying silicon were relieved dramatically after the lead bumps were removed from the wafer, which confirms that the bumps are indeed a major source of strain in the underlying Si. Finite element modeling (FEM) has also been performed in two-dimensional (2-D) plane strain mode. The magnitudes and spatial distribution of the stresses after the reflow process are in good agreement with the SXRT results.

Synchrotron X-ray topography of undoped VCz GaAs crystals

For the first time vapour pressure controlled Czochralski (VCz) monocrystals of semi-insulating (SI) GaAs, grown at IKZ Berlin, have been investigated by synchrotron X-ray topography. The X-ray topographs of a typical VCz sample, taken from the cylindrical part, show dislocation images resembling those of SI vertical gradient freeze-grown GaAs crystals. From the disappearance of the dislocation image in selected topographs it is concluded that the Burgers vector for most dislocations is parallel to . The main part proves to be of 60° type. The cellular structure, typical for liquid encapsulated Czochralski material, is not seen in the VCz samples. Large volumes up to 0.5 x 0.5 × 0.5 mm 3 are dislocation-free. The results are compared with etch pit density (EPD) measurements from the same crystals. The average EPD is (1-2) x 10 4 cm -2 . The minimum value along is 2 × 10 3 cm 2 .

Geometric linewidth and the impact of thermal processing on the stress regimes induced by electroless copper metallization for Si integrated circuit interconnect technology

Mechanical strains and stresses are a major concern in the development of copper-based on-chip metallization. Synchrotron x-ray topography (SXRT), micro-Raman spectroscopy, finite element modeling (FEM), and atomic force microscopy (AFM) have been used to examine the strain fields imposed by electroless Cu metallization on the underlying Si. As expected, we have observed enhanced strain regions close to the metal line edges. These strain fields tend to zero at annealing temperatures approaching 200 ° C, and thereafter the magnitudes of the strain fields at 300 ° C and 400 ° C are much higher, implying a return to a higher strain regime. Although the strain transition point is slightly different from the SXRT result, the FEM results confirm the existence of a zero-strain transition point as a function of thermal anneal. We have also examined the generated stress in Si as a function of Cu linewidth L. We have found that the stress sXX due to the electroless copper metallization is empirically related to the Cu linewidth in terms of an exponential distribution. For Cu linewidths less than 20 mm, the stress magnitudes increased with decreasing Cu linewidth due to the thermal stress in the absence of self-annealing, whereas the stress decreased with increasing linewidths in the range of 60‐ 100 mm due to a relief of the thermal stress possibly via the self-annealing effect. This self-annealing phenomenon was observed using AFM. It is observed that the stresses in the Si shifted to a compressive state after annealing at 400 ° C.

Examination of mechanical stresses in silicon substrates due to lead–tin solder bumps via micro-Raman spectroscopy and finite element modelling

Due to the fact that semiconductor devices have decreased significantly in geometry and increased enormously in electronic design complication, flip-chip packaging technology was launched to increase input/output count, improve electrical performance, reduce packaging size and be cost effective. The Intel®Pentium®III microprocessor uses the popular ball grid array (BGA) packaging technique. BGA is one of the most common flip-chip packaging techniques used for microprocessor applications. However, mechanical stresses induced by the flip-chip process are major concerns for the reliability of such devices. Micro-Raman spectroscopy (μRS) is a powerful technique for investigating the spatial extent of strain fields in microelectronic devices. In this study, the strain fields imposed on the underlying silicon substrate due to the lead–tin solder bump process in BGA packaging have been investigated in pre- and post-reflowed samples using μRS and finite element modelling (FEM). For pre-reflowed samples, an approximate uniaxial compressive stress of 200 MPa is developed near the edge of the under bump metallization (UBM). However, a tensile stress up to ~300 MPa is found for post-reflowed samples. Two-dimensional (2D) plane strain FEM has also been performed. The magnitudes and spatial distribution of the stresses after the reflow process are in good agreement with the micro-Raman results.

Determination of crystal misorientation in epitaxial lateral overgrowth of GaN

Epitaxial lateral overgrowth of GaN on Al2O3 using a SiO2 mask with different fill factors (ratio of stripe opening width to stripe period) is examined with synchrotron X-ray topography (SXRT) and X-ray diffraction (XRD) techniques. The crystal misorientation in the lateral overgrown region (wing) and the normal region (window region and beneath the seed layer) is determined with SXRT. The wings tilt asymmetrically around the window and the tilts increase as the fill factor increases. XRD measurements confirm the same wing tilt tendency as the fill factor changes. The average wing tilt reaches approximately 1600 arcsec measured using the X-ray rocking curve method at a fill factor of 0.625, but the maximum wing tilts can reach values as large as 2400 arcsec measured by SXRT when the fill factor is only 0.571. The significance of this is explained. The crystal misorientation in the normal region is approximately an order of magnitude less than the wing tilt. r 2002 Elsevier Science B.V. All rights reserved.

Quality Assessment of Sapphire Wafers for X-Ray Crystal Optics Using White Beam Synchrotron X-Ray Topography

The white beam Synchrotron X-Ray Topography (SXRT) technique was used to assess the quality of sapphire wafers grown by the Heat-Exchanger Method (HEM) and the Modified Czochralski Method (MCM). Sapphire is a potential new material for X-ray crystal optics, especially for use as Bragg backscattering mirrors for X-rays and Mossbauer radiation. The dislocation distribution, dislocation density and Burgers vector of selected dislocations and stacking faults in the sapphire wafers were studied. A correlation between the sapphire quality and its performance as an X-ray backscattering mirror was established in this paper. The results reveal the high quality of the inspected HEM sapphire wafers and their subsequently improved performance as Bragg backscattering mirrors.

Misfit dislocations in GaAsN-GaAs interface

Highly strained GaAsN layers were grown on GaAs by metal-organic vapor phase epitaxy and studied by synchrotron X-ray topography and X-ray diffraction. The critical thickness for misfit dislocation formation of the GaAs0.965N0.035 epitaxial layer on GaAs was found to be between 50 and 80 nm. In layers thicker than the critical thickness a misfit dislocation network was observed. The network was found to be isotropic and uniform. The relaxation of the strained epilayer begins through the misfit-dislocation generation and continues via formation of cracks. The cracks are not distributed as uniformly as misfit dislocations.

Characterization of AlN/AlGaN/GaN:C heterostructures grown on Si(111) using atom probe tomography, secondary ion mass spectrometry, and vertical current-voltage measurements

Complementary studies of atom probe tomography, secondary ion mass spectrometry, and vertical current-voltage measurements are carried out in order to unravel the influence of C-doping of GaN on the vertical leakage current of AlN/AlGaN/GaN:C heterostructures. A systematic increment of the vertical blocking voltage at a given current density is observed in the structures, when moving from the nominally undoped conditions—corresponding to a residual C-background of ∼1017 cm−3—to a C-content of ∼1019 cm−3 in the GaN layer. The value of the vertical blocking voltage saturates for C concentrations higher than ∼1019 cm−3. Atom probe tomography confirms the homogeneity of the GaN:C layers, demonstrating that there is no clustering at C-concentrations as high as 1020 cm−3. It is inferred that the vertical blocking voltage saturation is not likely to be related to C-clustering.

The evaluation of mechanical stresses developed in underlying silicon substrates due to electroless nickel under bump metallization using synchrotron X-ray topography

The switch-over to the use of flip-chip Si integrated circuit bonding techniques has been driven by a need to develop higher power and lower voltage devices, capable of carrying larger currents with greater reliability. With the increased use of solder bump interconnections, an understanding of the behaviour of commonly used electroless nickel under bump metallization (UBM) layers is becoming ever more crucial. The aim of this paper is to evaluate the usefulness of white beam synchrotron X-ray topography (WBSXRT) for non-destructive evaluation of the induced mechanical stresses on Si substrates for different Ni(P) based UBM sizes and thicknesses. It is shown that WBSXRT is a powerful tool for non-destructively mapping strain and/or defect distributions within the underlying silicon substrate. Using this technique, it was also found that the crystalline misorientation induced in the underlying silicon is increased for larger UBM diameters. Stress magnitudes in the Si substrate directly under the UBM can reach values as high as 260MPa.