Lawrence M. Devito

A 150 mW, 155 MHz phase locked loop with low jitter VCO

This paper describes a 155 MHz clock recovery phase locked loop (PLL) for use in fiber optic serial data communication systems. The PLL incorporates a low jitter voltage controlled ring oscillator. Some of the inherent limitations of the ring architecture, as well as design techniques for dealing with those limitations, are discussed. The PLL chip has been fabricated in a dielectrically isolated complementary bipolar process, occupies a die area of 2 mm/spl times/3 mm, and consumes 150 mW operating from a 5V supply.<<ETX>>