Seok-Hoon Kim

Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices

High-k/metal gate (HKMG) compatible high performance Source/Drain (S/D) stress-memorization-technology (SMT) is presented. Channel stress generated by SMT can be simulated by using mask-edge dislocation model, which is consistent with the measured actual channel stress. Extremely deep pre-amorphization-implant (PAI) for SMT creates multiple mask-edge dislocations under S/D region, which enhances short-channel mobility by 40∼60%. Finally, more than 10% short channel drive current gain is achieved with additional S/D extension optimization.

A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches

In this paper, a power efficient vertex processor for mobile graphics applications is presented. A four-threaded and four-issue expanded VLIW datapath with a quad-float vertex texture fetcher is proposed by exploiting graphics specific characteristics after evaluation of several candidate architectures. Instruction-level power control methods such as operand sharing and writeback re-allocation along with operand isolations and gated clocks result in 40.4% and 82% reduction in energy dissipation and energy delay product compared to the most widely used single threaded SIMD. The proposed processor with the optimized datapath and vertex caches implemented in a 0.18- mum 1P4M CMOS process achieves 186-Mvertices/s geometry performance which is the best result among the processors that are IEEE-754 compliant.

Simultaneous intermediate-view interpolation and multiplexing algorithm for a fast lenticular display

Lenticular displays are a promising form of autostereoscopic technology and several products have recently been commercialized. For lenticular displays, typically several views of a scene are acquired from different viewpoints, or are generated by using depth information. If the depth information of a scene is known, then it is possible to easily generate several intermediate views simply by using the stereo image pair and depth information. The paper presents a simple method to cor- rect the lenticular alignment error by compensating the correction coef- ficients to the viewpoint determination formula. For the realization of a fast lenticular display and removal of image distortion and artifacts, the proposed algorithm simultaneously performs intermediate floating- pointview interpolation and multiplexing on the scanline using the left- view and right-view images and depth information. Experimental results show that lenticular images having considerably reduced distortion and artifacts are generated by using the proposed algorithm.

A Unified Graphics and Vision Processor With a 0.89 /spl mu/W/fps Pose Estimation Engine for Augmented Reality

A unified vision and graphics processor with three layers is shown to provide a fast pipeline for augmented reality. In the image-level layer, a 153.6 GOPS massively parallel processing unit with eight SIMD processors, each containing 128 processing elements, performs highly data-parallel operations. In the sub-image layer, a rasterizer and a pixel arranger respectively generate and reduce data-level parallelism. In the descriptor-level layer, a pose estimation engine executes sequential programs. Our processor can provide images for augmented reality at 100 fps, for a power consumption of 413 mW. This is 39% faster than a comparable smartphone implementation. Our chip is fabricated in a 0.18 μm CMOS process and contains 0.95 M gates.

Homogeneous Stream Processors With Embedded Special Function Units for High-Utilization Programmable Shaders

We embed special function units (SFUs) in homogeneous stream processors (SPs) within a graphics processing unit (GPU), to improve its performance in running modern programmable shaders, which make poor use of a single-instruction multiple-data (SIMD) architecture. We also compact instructions, so as to reduce the size of the instruction memory, and reduce area requirements by using a partial SFU in SPs, and a lookup table which is shared between multiple SFUs. The result is an increase of 88% in utilization and a reduction in the normalized area-delay product of 27%, compared to a baseline SIMD architecture. We verified our architecture on an field-programmable gate-array evaluation platform with an ARM9 host processor and a full 3-D graphics pipeline.

A 116 fps/74 mW Heterogeneous 3D-Media Processor for 3-D Display Applications

In this paper, a heterogeneous 3D-media processor is presented, which supports all 3-D display applications by combining a 3-D display IP with a 3-D graphics IP and a stereo video decoder. For mobile environments, adaptive power management scheme is proposed, which saves power consumption up to 186 mW by turning off idle functional blocks based on a target application, a target performance, and the run-time ratio between different IPs. As a result, the minimum power consumption of the processor is only 15 mW, while the overall power consumption is 201 mW. As well as the reduction of power consumption, this work shows impressive performance improvement. The proposed fast modulo operators and adopted division-free algorithm reduces the critical latencies of 3-D display image processing. The proposed fast datapath with parallel architecture increase synthesis rate up to 116 fps which is 17 times faster than a previous work. In addition, reordered operation sequence fixes memory bandwidth regardless of the number of images to be produced. In the 3-D graphics IP and the decoding IP, redundant datapath are merged using an IEEE 754 compliant floating-point vector unit to save both chip area and power consumption, which even reduces the critical latency by 30%.

A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine

A 3D display processor with a programmable 3D graphics rendering engine is implemented. The integrated rendering engine supports Pixel Shader 3.0 and OpenGL ES 2.0. A 3D image synthesis engine generates 3D images at 36fps. The die contains 1.74M gates and occupies 5times5mm2 in 0.18mum CMOS and dissipates 379mW at 1.8V.

A 36 fps SXGA 3-D Display Processor Embedding a Programmable 3-D Graphics Rendering Engine

In this paper, a 3D display processor embedding a programmable 3D graphics rendering engine is proposed. The proposed processor combines a 3D graphics rendering engine and a 3D image synthesis engine to support both true realism and interactivity for the future multimedia applications. Using high coherence between 3D graphics data and 3D display inputs, both pipelines are merged by sharing buffers such that a 3D display engine directly uses the output of a 3D graphics rendering engine. The merged architecture has synergetic coupling effects such as freely providing various rendering effects to 3D images and easily computing disparities without complex extraction processes. In the 3D image synthesis engine, we adopt view interpolation algorithm and propose real-time synthesis method, pixel-by-pixel process. The view interpolation algorithm reduces the number of images to be rendered, resulting in the reduction of external memory size to 64.8% compared to conventional synthesis process. The proposed pixel-by-pixel process synthesizes 3D images at 36 fps through bandwidth reduction of 26.7% and decreases internal memory size to 64.2% compared to typical image-by-image process. The 3D graphics rendering engine is programmable and supports the instruction sets of the latest 3D graphics standard APIs, Pixel Shader 3.0 and OpenGL|ES 2.0. The die contains about 1.7 M transistors, occupies 5 mm times 5 mm in 0.18 mum CMOS and dissipates 379 mW at 1.85 V.

A graphics and vision unified processor with 0.89µW/fps pose estimation engine for augmented reality

In many ways, 3D graphics and vision processing are inverse operations. Graphics processing generates pixels from descriptors, while vision generates descriptors from pixels [1]. Since augmented reality (AR) requires both graphics and vision abilities (Fig. 18.6.1), we report a unified processor for graphics, vision, and pose estimation for marker tracking. To process both graphics and vision simultaneously, we use 4 key features: (1) 6-way VLIW datapath design of processing elements, (2) reconfigurable processing elements for graphics and vision modes, (3) a pixel arranger for vision processing that has the inverse characteristic of a graphics rasterizer, and (4) a dedicated pose-estimation engine to generate graphics control data from vision processing. Using these methods, we achieve 371.9GOPS/W for full operation in a VGA image and 0.89µW/fps for pose estimation.

A Simultaneous View Interpolation and Multiplexing Method using Stereo Image Pairs for Lenticular Display

Nowadays, the slanted lenticular display becomes a representative one among the commercially introduced autostereoscopic displays. The paper presents a simple method to correct the lenticular alignment error by compensating the correction coefficients to the view number determination formula. Then, based on the corrected view numbers, the proposed algorithm simultaneously performs floating-point viewpoint generation and multiplexing on the scanline using the stereo image pairs and its depth information. Experimental results show that lenticular images, in which distortion and artifact due to lenticular alignment error are considerably reduced, are generated rapidly by using the proposed algorithm.