Daniel R. Knebel

A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs

Most existing power gating structures provide only one power-saving mode. We propose a novel power gating structure that supports both a cutoff mode and an intermediate power-saving and data-retaining mode. Experiments with test structures fabricated in 0.13-mum CMOS bulk technology show that our power gating structure yields an expanded design space with more power-performance tradeoff alternatives.

Minimizing inductive noise in system-on-a-chip with multiple power gating structures

A multiple power domain strategy in which each power domain has an independent power gating structure is an effective means for reducing leakage power consumption in a system-on-a-chip. During an individual power gating structure power-mode transition, however, serious inductive noise is introduced that may affect normal operation of neighboring circuits. We present a novel power gating structure in which inductive noise is reduced through gradual turn-on and turn-off its sleep transistor. Experimental simulation results with PowerSpice fixtured in different package models demonstrate the effectiveness of the proposed power gate switching noise reduction technique.

The importance of inductance and inductive coupling for on-chip wiring

The importance of inductance and inductive coupling for accurate delay and crosstalk prediction in on-chip interconnections is investigated experimentally for the top three layers in a five-layer wiring structure and guidelines are formulated. In-plane and between-plane crosstalk and delay dependence on driver and receiver circuit device sizes and line lengths and width are analyzed with representative CMOS circuits. Simplified constant-parameter, distributed coupled-line RLC-circuit representation that approximates the waveforms predicted with frequency-dependent line parameters is shown to be feasible.

Diagnosis and characterization of timing-related defects by time-dependent light emission

Technological advances such as flip-chip packaging, multiple hierarchical wiring planes, and ultra-high frequencies reduce the effectiveness of conventional diagnostic techniques. It has recently been demonstrated that light pulses emitted during circuit switching can be used to characterize the behaviour of integrated circuits. In this paper, a new method of circuit characterization using this technique is described. An example of the diagnosis of a timing failure caused by a resistive path to a single transistor is described.

Low-power circuits and technology for wireless digital systems

As CMOS technology scales to deep-submicron dimensions, designers face new challenges in determining the proper balance between aggressive high-performance transistors and lower-performance transistors to optimize system power and performance for a given application. Determining this balance is crucial for battery-powered handheld devices in which transistor leakage and active power limit the available system performance. This paper explores these questions and describes circuit techniques for low-power communication systems which exploit the capabilities of advanced CMOS technology.

Diagnostic techniques for the IBM S/390 600 MHz G5 microprocessor

This paper describes strategies and techniques used to diagnose failures in the IBM 600 MHz G5 (Generation 5) CMOS microprocessor and associated cache chips. Time-to-market pressure demands quick diagnostic turnaround time while the complexity, density, cycle time, and technology issues of the hardware increase the difficulty of diagnosis. Since G5 first silicon, intense diagnostics and physical failure analysis (PFA) have successfully identified the root cause of many failures, including examples of process, design, and random manufacturing defects. This success is attributed to the three techniques described in this paper. For each technique, an example is presented to demonstrate its effectiveness.

Circuit design techniques for the high-performance CMOS IBM S/390 parallel enterprise server G4 microprocessor

This paper describes the circuit design techniques used for the IBM S/390® Parallel Enterprise Server G4 microprocessor to achieve operation up to 400 MHz. A judicious choice of process technology and concurrent top-down and bottom-up design approaches reduced risk and shortened the design time. The use of timing-driven synthesis/placement methodologies improved design turnaround time and chip timing. The combined use of static, dynamic, and self-resetting CMOS (SRCMOS) circuits facilitated the balancing of design time and performance return. The use of robust PLL design, floorplanning, and clock distribution minimized clock skew. Innovative latch designs permitted performance optimization without adding risk. Microarchitecture optimization and circuit innovations improved the performance of timing-critical macros. Full custom array design with extensive use of SRCMOS circuit techniques resulted in an on-chip L1 cache having 2.0-ns cycle time.

Picosecond imaging circuit analysis of the POWER3 clock distribution

Picosecond imaging circuit analysis (PICA) is shown to be a valuable means for measuring internal timing of microprocessors operating at speed. In this paper, PICA is applied to the analysis of delays and skew of the IBM POWER3 64b microprocessor clock distribution.

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits

Systems-on-chips (SoCs) that combine digital and high-speed communication circuits present new opportunities for power-saving designs. This results from both the large number of system specifications that can be traded off to minimize overall power and the inherent low capacitance of densely integrated devices. As shown in this paper, aggressively scaled silicon-on-insulator (SOI) CMOS is a promising technology for SoCs for several reasons: Transistor scaling leads to active power reduction in the sub-50-nm-channel-length regime, standard interconnect supports the high-quality passive devices essential to communications circuitry, and high-speed analog circuits on SOI are state of the art in terms of both performance and power dissipation. We discuss the migration of a complete digital circuit library from bulk to SOI to prove that SOI CMOS supports ASIC-style as well as fully custom circuit design.

The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA)

This paper will provide a case study of a particularly difficult debug problem (the Holey Shmoo problem) which developed while designing the IBM System/390 G6 637 MHz microprocessor chip. Resolution of this problem involved the use of some of todays newest DFD/DFT and diagnostics techniques. The discussion of the Holey Shmoo problem and its debug will serve to highlight and demonstrate some of these advanced techniques.