Leland Chang

Sub 50-nm FinFET: PMOS

High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOS FinEET has an I/sub dsat/ of 410 /spl mu/A//spl mu/m (or 820 /spl mu/A//spl mu/m depending on the definition of the width of a double-gate device) at Vd=Vg=1.2 V and Tox=2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to 10-nm gate length.

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I/sub dsat/ of 820 /spl mu/A//spl mu/m at V/sub ds/=V/sub gs/=1.2 V and T/sub ox/=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm.

Extremely scaled silicon nano-CMOS devices

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.

Gate length scaling and threshold voltage control of double-gate MOSFETs

In the nanoscale regime, the double-gate MOSFET can provide superior short-channel behavior. For this structure, device scaling issues are explored. Gate length scaling will be limited by the ability to control off-state leakage current due to quantum tunneling and thermionic emission between the source and drain as well as band-to-band tunneling between the body and drain. Lateral S/D doping abruptness requirements for gate length scaling are examined. V/sub T/ control will be challenging as a single gate material for both NMOS and PMOS devices cannot provide low yet symmetrical V/sub T/s. CMOS integration will thus require dual gate workfunction tuning, channel doping, or asymmetrical double-gates to adjust V/sub T/. Advantages of using alternative channel materials to facilitate scaling are investigated.

Sub-60-nm quasi-planar FinFETs fabricated using a simplified process

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 /spl mu/A//spl mu/m (or 1 mA//spl mu/m, depending on the definition of the width of the double-gate device) for V/sub g/-V/sub t/=V/sub d/=1 V. The electrical gate oxide thickness in these devices is 21 /spl Aring/, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness.

FinFET process refinements for improved mobility and gate work function engineering

Process refinements to improve the performance of FinFETs are described. Hydrogen annealing is shown to provide high surface quality on etched fin sidewalls for improved drive current and noise performance. Appropriate V/sub t/ is achieved in lightly doped p-channel FinFETs using Molybdenum (Mo) as the gate-electrode material for the first time. Multiple values of V/sub t/ are achieved via gate work function engineering by selective implantation of Mo.

Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs

The impact of energy quantization on gate tunneling current is studied for double-gate and ultrathin body MOSFETs. Reduced vertical electric field and quantum confinement in the channel of these thin-body devices causes a decrease in gate leakage by as much as an order of magnitude. The effects of body thickness scaling and channel crystallographic orientation are studied. The impact of threshold voltage control solutions, including doped channel and asymmetric double-gate structures is also investigated. Future gate dielectric thickness scaling and the use of high-/spl kappa/ gate dielectrics are discussed.

FinFET-a quasi-planar double-gate MOSFET

The quasi-planar FinFET structure has device characteristics similar to those of the conventional MOSFET. Inserting FinFET into CMOS technology requires no change in circuit architecture or layout/design tools, providing a smooth transition to post-planar CMOS technology. 2D mixed-mode simulations show FinFET circuit performance exceeds that of advanced single gate MOSFETs.

Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs

The impact of energy quantization on gate tunneling current is studied for double-gate and ultra-thin body MOSFETs. The lower vertical electric field in the channel of these thin-body devices causes a reduction in gate leakage by as much as an order of magnitude. The additional effects of channel doping and high-k dielectrics are also investigated.

Quasi-planar NMOS FinFETs with sub-100 nm gate lengths

Double-gate MOSFETs alleviate short channel effects and allow for more aggressive device scaling. Simulations have shown that scaling double-gated devices can reach 10 nm. In the past, process complexity has prevented serious development of a scalable double-gate device. In 1998, Hisarnoto et al. introduced a FinFET process that provided a method of fabricating devices with promising performance and scalability. Using a single poly layer across a silicon fin to form both gates in the double-gate structure, the FinFET benefits from having equally-sized, self-aligned gates. In this work, we have revamped the FinFET process flow to make it simpler. This improved process flow still has the self-aligned, double-gate advantage without suffering from extra gate-to-drain overlap capacitance.