Nick Lindert

Ultrathin-body SOI MOSFET for deep-sub-tenth micron era

A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with <5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance.

Sub-60-nm quasi-planar FinFETs fabricated using a simplified process

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 /spl mu/A//spl mu/m (or 1 mA//spl mu/m, depending on the definition of the width of the double-gate device) for V/sub g/-V/sub t/=V/sub d/=1 V. The electrical gate oxide thickness in these devices is 21 /spl Aring/, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness.

FinFET-a quasi-planar double-gate MOSFET

The quasi-planar FinFET structure has device characteristics similar to those of the conventional MOSFET. Inserting FinFET into CMOS technology requires no change in circuit architecture or layout/design tools, providing a smooth transition to post-planar CMOS technology. 2D mixed-mode simulations show FinFET circuit performance exceeds that of advanced single gate MOSFETs.

Ultra-thin body SOI MOSFET for deep-sub-tenth micron era

A 40nm-gate-length ultra-thin body (UTB) nMOSFET is demonstrated. A self-aligned thin body SOI device has previously been proposed for suppressing the short channel effect. UTB structure can eliminate the punchthrough path between source and drain and provide a more evolutionary alternative to the double-gate MOSFET for deep-sub-tenth micron technology. The advantage of using UTB is illustrated through device simulation (with the aid of Silvaco ATLAS) using simple doping profiles for the body and S/D (simple Gaussian).

Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages

We have investigated circuit options to surpass the 1 V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on- and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed.

Quasi-planar NMOS FinFETs with sub-100 nm gate lengths

Double-gate MOSFETs alleviate short channel effects and allow for more aggressive device scaling. Simulations have shown that scaling double-gated devices can reach 10 nm. In the past, process complexity has prevented serious development of a scalable double-gate device. In 1998, Hisarnoto et al. introduced a FinFET process that provided a method of fabricating devices with promising performance and scalability. Using a single poly layer across a silicon fin to form both gates in the double-gate structure, the FinFET benefits from having equally-sized, self-aligned gates. In this work, we have revamped the FinFET process flow to make it simpler. This improved process flow still has the self-aligned, double-gate advantage without suffering from extra gate-to-drain overlap capacitance.

Quasi-planar FinFETs with selectively grown germanium raised source/drain

Double-gate MOSFETs are attractive because they can be scaled to the shortest gate length for a given gate oxide thickness. Recent studies suggest that double gate devices can meet performance requirements down to 10 nm gate length. The FinFET was introduced and is a promising double-gate structure. A simplified, quasi-planar version of the FinFET exhibiting, excellent performance was presented. Short channel effects can be suppressed in the FinFET provided that the gate length is at least 1.4 times the fin thickness. The source/drain (S/D) thin fin extension regions are highly resistive so it is essential to minimize the length of the S/D thin fin extensions. In this work, we combine the simplicity of the new FinFET process flow with a selective Ge growth technique to present the first raised S/D quasi-planar FinFET devices.

Comparison of GIDL in p/sup +/-poly PMOS and n/sup +/-poly PMOS devices

Gate-induced-drain-leakage (GIDL) in LDD p-MOSFETs has been studied. The emphasis of this paper is on the comparison of GIDL in p/sup +/-poly PMOS versus n/sup +/-poly PMOS devices. Measurements show that the GIDL is less severe in p/sup +/-poly devices. Clarification for modeling GIDL in devices with different drain structures is also provided.