Tim LaRocca

324GHz CMOS Frequency Generator Using Linear Superposition Technique

This paper presents CMOS for terahertz applications, substantially extended the operation range of deep-submicron CMOS by using a linear superposition method, in which we have realized a 324GHz frequency generator in 90nm digital CMOS with 4GHz tuning range under 1V supply voltage.

Terahertz CMOS Frequency Generator Using Linear Superposition Technique

A low Terahertz (324 GHz) frequency generator is realized in 90 nm CMOS by linearly superimposing quadruple (N=4) phase shifted fundamental signals at one fourth of the output frequency (81 GHz). The developed technique minimizes the fundamental, second and third order harmonics without extra filtering and results in a high fundamental-to-4 th harmonic signal conversion ratio of 0.17 or -15.4 dB. The demonstrated prototype produces a calibrated -46 dBm output power when biased at 1 V and 12 mA with 4 GHz tuning range and extrapolated phase noise of -91 dBc/Hz at 10 MHz frequency offset. The linear superposition (LS) technique can be generalized for all even number cases (N=2k, where k=1,2,3,4,...,n) with different tradeoffs in output power and frequency. As CMOS continues to scale, we anticipate the LS N=4 VCO to generate signals beyond 2 Terahertz by using 22 nm CMOS and produce output power up to -1.5 dBm with 1.7% power added efficiency with an LS VCO + Class-B Power Amplifier cascaded circuit architecture.

60 GHz CMOS Amplifiers Using Transformer-Coupling and Artificial Dielectric Differential Transmission Lines for Compact Design

57-65 GHz differential and transformer-coupled power and variable-gain amplifiers using a commercial 90 nm digital CMOS process are presented. On-chip transformers combine bias, stability and input/interstage matching networks to enable compact designs. Balanced transmission lines with artificial dielectric strips provide substrate shielding and increase the effective dielectric constant up to 54 for further size reduction. Consequently, the designed three-stage power amplifier occupies only an area of only 0.15 mm2. Under a 1.2 V supply, it consumes 70 mA and obtains small-signal gains exceeding 15 dB, saturated output power over 12 dBm and associated peak power-added efficiency (PAE) over 14% across the band. The variable-gain amplifier, based on the same principle, achieved a peak gain of 25 dB with 8 dB of gain variation.

Millimeter-wave CMOS digital controlled artificial dielectric differential mode transmission lines for reconfigurable ICs

Digital control of the effective dielectric constant of a differential mode transmission line is shown up to 60GHz in standard CMOS technology. The effective dielectric constant is shown to increase from 5 to over 50 for the fixed artificial dielectric case. The digital controlled artificial dielectric transmission line (DiCAD) uses MOS switches to dynamically control the phase. DiCAD achieves 50% of the physically available tuning range with effective dielectric constants varying between 7 and 28. Measured results favorably agree with full-wave electromagnetic simulations.

60GHz CMOS differential and transformer-coupled power amplifier for compact design

A 57-65 GHz differential and transformer-coupled power amplifier using a commercial 90 nm digital CMOS process is presented. On-chip transformers combine bias, stability and input/interstage matching networks for a compact design with an area of 0.15 mm2. The three-stage amplifier consumes 70 mA under 1.2 V supply voltage. The small-signal gain generally exceeds 15 dB with saturated output power levels over 12 dBm and associated peak power-added efficiency (PAE) greater than 20% (14% across the band).

CMOS digital controlled oscillator with embedded DiCAD resonator for 58–64GHz linear frequency tuning and low phase noise

A digital controlled artificial dielectric (DiCAD) differential transmission line is embedded in 90nm CMOS to digitally tune a 58–64GHz DCO. DiCAD varies εr,eff from 18.8 to 32.5. A shunt open stub DiCAD provides discrete capacitive tuning with 13.1° S11 phase variation. The core oscillator is an inductively loaded differential, cross-coupled NMOS pair. Large nonlinear varactors are avoided, and the phase noise is better than −90dBc/Hz at 1MHz offset. Linear tuning bandwidth of 9.3% with a 61GHz center frequency occupying 0.01mm2 is achieved. Power consumption is 8.52mW with 1.2V.

Embedded DiCAD linear phase shifter for 57–65GHz reconfigurable direct frequency modulation in 90nm CMOS

A digitally controlled artificial dielectric (DiCAD) differential transmission line is designed to perform agile linear phase shift over 100° with thermometer-coded 16step control. It also operates with a 16 gain-step VGA to enable re-configurable and direct-frequency modulation at 60GHz with 2562 states (1.1° angular and 0.0007 magnitude resolutions) and −31dB static EVM for multiple PSK/QAM modulations. The modulator uses 0.33mm2 core area in 90nm CMOS and consumes 10mA at 1V.

A 64QAM 94GHz CMOS transmitter SoC with digitally-assisted power amplifiers and thru-silicon waveguide power combiners

A 94GHz 64QAM 1Gbps reconfigurable system-on-chip (SoC) CMOS transmitter with digitally-assisted power amplifiers (DAPA) and back-etched thru silicon waveguide power combiners is presented. The SoC includes a 7M gate ASIC with reconfigurable digital modulation and transmit pre-coding. The ASIC feeds two 10b 1.4GHz current-steering DACs followed by a direct conversion IQ modulator driving eight DAPAs. A 64QAM signal achieves 3.9% EVM with 50dBc ACPR at 94GHz. The data rate is 1.05Gbps and the output power exceeds 10dBm. DC power is 2.1W. The SoC uses IBM 12SOI CMOS.

A 45GHz CMOS transmitter SoC with digitally-assisted power amplifiers for 64QAM efficiency improvement

A 45GHz 64QAM system-on-chip (SoC) CMOS transmitter with digitally-assisted power amplifiers (DAPA) is presented. The SoC includes a 7M gate ASIC with 9b reconfigurable symbol mapping, 8X upsampling, 161tap pulse shape filtering, IQ imbalance correction and DAPA envelope/time estimation. The ASIC feeds two 10b IQ current-steering DACs and active IQ modulator. A unique transformer splitting up converter drives eight parallel combined DAPAs. The chip is packaged in aluminum housing with WR22 outputs. A 64QAM signal achieves 1.8% EVM with 33dBc ACPR at 45GHz. The data rate is 450Mbps and the integrated output power exceeds -10dBm.

Simultaneous linearity and efficiency enhancement of a digitally-assisted GaN power amplifier for 64-QAM

The first dynamic 4-bit, digitally-assisted GaN high power amplifier (DAPA) system transmitting 7.68Msymbol/s with 64-QAM modulation is presented. An FPGA is programmed to generate the pulse-shaped 64-QAM signal, perform envelope estimation, and time-align the RF and digital control signals arriving at the DAPA. A high-speed, level-shifting circuit converts the FPGAs low-voltage differential signaling (LVDS) DAPA control signals into single-ended logic levels required for the depletion-mode GaN HEMT DAPA auxiliary cells. Measured results show 9.6% DC power savings, 23% improved PAE, and 23% higher output power at 4% EVMRMS compared to the static PA configuration.