Leo C. N. de Vreede

A Wideband 2

This paper presents a wideband 2 ×13-bit in-phase/quadrature-phase (I/Q) RF digital-to-analog converter-based all-digital modulator realized in 65-nm CMOS. The isolation between I and Q paths is guaranteed employing 25% duty-cycle differential quadrature clocks. With a 1.3-V supply and an on-chip power combiner, the digital I/Q transmitter provides more than 21-dBm RF output power within a frequency range of 1.36-2.51 GHz. The peak RF output power, overall system, and drain efficiencies of the modulator are 22.8 dBm, 34%, and 42%, respectively. The measured static noise floor is below -160 dBc/Hz. The digital I/Q RF modulator demonstrates an IQ image rejection and local oscillator leakage of -65 and -68 dBc, respectively. It could be linearized using either of the two digital predistortion (DPD) approaches: a memoryless polynomial or a lookup table. Its linearity is examined using single-carrier 4/16/64/256/1024 quadrature amplitude modulation (QAM), as well as multi-carrier 256-QAM orthogonal frequency-division multiplexing baseband signals while their related modulation bandwidth can be as high as 154 MHz. Employing DPD improves the third-order intermodulation product (IM3) by more than 25 dB, while the measured error vector magnitude for a “single-carrier 22-MHz 64-QAM” signal is better than -28 dB.

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This paper describes the design and implementation of a package-integrated Chireix outphasing RF switch-mode power amplifier (PA). The optimum loading conditions, based on class E, and the Chireix compensation elements are provided to the active devices by a dedicated low-loss bondwire-based transformer power combiner that enables a very small form factor and low cost. The realized prototype achieved 70.6-W peak power with 73% peak drain efficiency at 2.3 GHz and 28 V, and up to 81% peak drain efficiency at 2.2 GHz and 20 V. When operated for maximum power at 28 V, it reached 53.5%/43.5% average drain/total efficiency for a 9.6-dB peak-to-average-power-ratio W-CDMA signal at 2.3 GHz with low ACLR1/2 levels ( -49/ -56 dBc after memoryless digital predistortion). Moreover, from 2.1 to 2.4 GHz, the realized PA demonstrated more than 50% drain efficiency across > 260, > 160, and > 80 MHz at 6-, 8-, and 10-dB back-off, respectively.

13-bit All-Digital I/Q RF-DAC

We present a technology for the manufacturing of silicon-filled integrated waveguides enabling the realization of low-loss high-performance millimeter-wave passive components and high gain array antennas, thus facilitating the realization of highly integrated millimeter-wave systems. The proposed technology employs deep reactive-ion-etching (DRIE) techniques with aluminum metallization steps to integrate rectangular waveguides with high geometrical accuracy and continuous metallic side walls. Measurement results of integrated rectangular waveguides are reported exhibiting losses of 0.15 dB/ λg at 105 GHz. Moreover, ultra-wideband coplanar to waveguide transitions with 0.6 dB insertion loss at 105 GHz and return loss better than 15 dB from 80 to 110 GHz are described and characterized. The design, integration and measured performance of a frequency scanning slotted-waveguide array antenna is reported, achieving a measured beam steering capability of 82 ° within a band of 23 GHz and a half-power beam-width (HPBW) of 8.5 ° at 96 GHz. Finally, to showcase the capability of this technology to facilitate low-cost mm-wave system level integration, a frequency modulated continuous wave (FMCW) transmit-receive IC for imaging radar applications is flip-chip mounted directly on the integrated array and experimentally characterized.

A Package-Integrated Chireix Outphasing RF Switch-Mode High-Power Amplifier

This paper elaborates on the recently introduced concept of an all-digital RF I/Q modulator. Orthogonal summation and design procedure of the power combining network are explained in more detail. A 65 nm CMOS prototype is implemented based on this concept. The prototype achieves 12.6 dBm peak output power and 20% peak drain efficiency at 2 GHz. While providing 6 dBm output power, the error vector magnitude (EVM) is 3.7%.

Silicon-Filled Rectangular Waveguides and Frequency Scanning Antennas for mm-Wave Integrated Systems

State-of-the-art wireless communication radios are implemented in deep-submi-cron CMOS, including the RF power amplifiers (PAs). However, in wireless infrastructure systems, the RF PA is often realized in an LDMOS or a compound technology to obtain the required large output powers. For next-generation reconfigurable infrastructure systems, the switch-mode PAs (SMPA) seem to offer the required flexibility for multiband multimode transmitters. In order to interface the high-power devices of the SMPA with the digital CMOS blocks of the transmitter, a wideband RF CMOS driver capable to generate high voltage (HV) swings is required. In this way, digital signal processing can be directly applied to control the required input pulse shapes of the SMPA.

Orthogonal summing and power combining network in a 65-nm all-digital RF I/Q modulator

We propose a novel digital I/Q modulator implemented in 65 nm CMOS technology. Using in-phase (I) and quadrature-phase (Q) clock signals with a 25% duty cycle, the modulator can directly construct the RF output signal using four transistor switch banks with a power combiner. The circuit achieves 12.6 dBm peak output power and 20% peak drain efficiency at 2 GHz. While providing 6 dBm output power, the error vector magnitude (EVM) is 3.7% and could be used as pre-driver or final transmit stage. The first ever all-digital I/Q RF-DAC prototype is thus experimentally demonstrated.

A 65nm CMOS pulse-width-controlled driver with 8V pp output voltage for switch-mode RF PAs up to 3.6GHz

This paper presents a 2×13-bit I/Q RF-DAC-based all-digital modulator realized in 65 nm CMOS. The proposed quadrature up-converter uses a 25% duty-cycle clock to isolate the in-phase (I) and quadrature-phase (Q) modulating signals before combining. Using a 1.2 V supply and an on-chip power combiner, the modulator provides more than 21 dBm RF output power within a frequency range of 1.36 to 2.51 GHz. The peak RF output power, overall system and drain energy efficiencies of the modulator are 22.3 dBm, 31.5%, and 39.7%, respectively. Applying digital predistortion (DPD), 64 & 256 constellation points are measured with EVM better than -30 dB. The measured noise floor is below -160 dBc/Hz, with an IQ image rejection and LO leakage of -65 and -63 dBc, respectively. Its linearity has been evaluated with WCDMA modulation. Using DPD, the linearity improves by more than 15 dB.

A 2-GHz digital I/Q modulator in 65-nm CMOS

A mixed-signal approach for “real-time”, fully-controlled, load-pull parameters sweeps is presented. The proposed approach permits high-speed sweeping of any combination of parameters, e.g. input power and fundamental and/or harmonic source or load termination, enabling at the same time full control of all other source and load terminations provided to the device-under-test. Using this method, a very efficient tool is created for high-speed large-signal device characterization, which can mimic realistic circuit conditions not only for single-tone signals, but also for wide-band complex modulated signals. The capabilities of the realized system are demonstrated by characterizing a NXP Gen 6 LDMOS device.

A 2×13-bit all-digital I/Q RF-DAC in 65-nm CMOS

A high-power class-E Chireix outphasing RF power amplifier integrated inside a transistor package is described. The optimum class-E loading conditions and the Chireix compensation elements are provided to the active devices by a dedicated ultra-low loss bondwire-based transformer power combiner that enables a very small form factor and low cost. The realized prototype achieves 70.6 W peak power with 73% peak drain-efficiency at 2.3 GHz, and up to 81% peak drain-efficiency for slightly lower power at 2.2 GHz. When operated for maximum power, it reaches 53.5%/43.5% average drain-/total-efficiency for a 9.6 dB PAR W-CDMA signal at 2.3 GHz with low ACLR1/2 levels (-49/-56 dBc after memory-less DPD).

A mixed-signal approach for high-speed fully controlled multidimensional load-pull parameters sweep

The capabilities of active load-pull are extended to be compatible with the characterization requirements of high-power base-station applications. The proposed measurement setup provides ultra-fast high-power device characterization for both CW, as well as, pulsed, duty-cycle controlled, operation. The realized system has the unique feature that it can handle realistic complex modulated signals like W-CDMA with absolute control of their reflection coefficients vs. frequency.