Marco Spirito

Adaptive Multi-Band Multi-Mode Power Amplifier Using Integrated Varactor-Based Tunable Matching Networks

This paper presents a multi-band multi-mode class-AB power amplifier, which utilizes continuously tunable input and output matching networks integrated in a low-loss silicon-on-glass technology. The tunable matching networks make use of very high Q varactor diodes (Q>100 @ 2 GHz) in a low distortion anti-series configuration to achieve the desired source and load impedance tunability. A QUBIC4G (SiGe, ft=50 GHz) high voltage breakdown transistor (VCBO=14 V, VCEO>3.6 V) is used as active device. The realized adaptive amplifier provides 13 dB gain, 27-28 dBm output power at the 900, 1800, 1900 and 2100 MHz bands. For the communication bands above 1 GHz optimum load adaptation is facilitated resulting in efficiencies between 30%-55% over a 10 dB output power control range. The total chip area (including matching networks) of the amplifier is 8 mm2

A 60GHz-band 1V 11.5dBm power amplifier with 11% PAE in 65nm CMOS

Sub-1V supplies limit the output voltage swing and saturated output power of an amplifier integrated in deep-submicron CMOS technology. Aside from absolute output power, power-added efficiency (PAE), stability and gain are also important power-amplifier (PA) design considerations. High reverse isolation between output and input is necessary to mitigate the effects of antenna mismatch, limit unwanted interference between circuit blocks on-chip and to promote stability. Efficiency of the PA is also paramount for portable consumer electronic applications operating from a battery, such as short-range Gb/s communication SoCs operating in the unlicensed bands around 60GHz. Aside from the 60GHz band, long-range collision-avoidance radar for automobiles (77/79GHz), and radio imaging (94GHz) are also potential applications for CMOS at mm-wave frequencies [1–4].

Active Harmonic Load–Pull With Realistic Wideband Communications Signals

A new wideband open-loop active harmonic load-pull measurement approach is presented. The proposed method is based on wideband data-acquisition and wideband signal-injection of the incident and device generated power waves at the frequencies of interest. The system provides full, user defined, in-band control of the source and load reflection coefficients presented to the device-under-test at baseband, fundamental and harmonic frequencies. The system capability to completely eliminate electrical delay allows to mimic realistic matching networks using their measured or simulated frequency response. This feature enables active devices to be evaluated for their actual in-circuit behavior, even on wafer. Moreover the proposed setup provides the unique feature of handling realistic wideband communication signals like multicarrier wideband code division multiple access (W-CDMA), making the setup perfectly suited for studying device performance in terms of efficiency, linearity and memory effects.

A 60-GHz Band 2

A 2×2 phased-array fully-differential transmitter IC with independent tuning of both vertical and horizontal polarizations realized in 65nm bulk CMOS is described in this paper. Phased-array transmitters increase the isotropic radiated power of a stand-alone transmitter over a single radiating element by 20*log10N dB, where N is the number of elements in the array [1,2]. They are well-suited to mm-Wave applications where spatial selectivity of the phased-array antenna compensates for beam directionality, and greater antenna gain helps offset path loss (88dB at 10m) that constrains 60GHz-band Tx/Rx link spans. Implementation in bulk CMOS technology favors co-integration of RF and baseband circuitry and the potential low production cost in volume for applications such as short-range Gb/s communication at (56 to 64GHz), collision avoidance radar (77/79GHz), and radio imaging (94GHz band).

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This paper addresses the properties of a surface-passivated (enhanced) high-resistivity silicon (HRS) substrate for use in monolithic microwave technology. The detrimental effects of conductive surface channels and their variations across the wafer related to the local oxide and silicon/silicon-dioxide interface quality are eliminated through the formation of a thin amorphous layer at the wafer surface. Without passivation, it is found that the surface channels greatly degrade the quality of passive components in HRS by masking the excellent properties of the bulk HRS substrate and by causing a spread in parameters and peak values across the wafer. Moreover, it is seen that the surface passivation leads to excellent agreement of the characteristics of fabricated components and circuits with those predicted by electromagnetic (EM) simulation based on the bulk HRS properties. This is experimentally verified for lumped (inductors and transformers) and distributed (coplanar waveguide, Marchand balun) passive microwave components, as well as for a traveling-wave amplifier, through which also the integration of transistors on HRS and the overall parameter control at circuit level are demonstrated. The results in this paper indicate the economically important possibility to transfer microwave circuit designs based on EM simulations directly to the HRS fabrication process, thus avoiding costly redesigns.

2 Phased-Array Transmitter in 65-nm CMOS

In this paper, we present an active harmonic load-pull system especially developed for the on-wafer linearity characterization/optimization of active devices with wideband modulated signals using the out-of-band linearization technique. Our setup provides independent control of the impedances at the baseband, fundamental, and second-harmonic frequencies presented to the input and output of the device under test. Furthermore, to enable realistic test conditions with wideband-modulated signals, the electrical delays in the load-pull system are kept as small as possible by implementing a novel loop architecture with in-phase quadrature modulators. We have achieved a phase variation of the reflection coefficient of only 5deg/MHz for both the fundamental and second-harmonic frequencies. We demonstrate the high potential of the system for the on-wafer evaluation of new technology generations by applying out-of-band linearization to heterojunction bipolar transistor (HBT) and laterally diffused metal-oxide-semiconductor (LDMOS) devices. For the HBT, we outline a game plan to obtain the optimum efficiency-linearity tradeoff. Finally, a record-high efficiency-linearity tradeoff was achieved (without digital predistortion) for an inverse class-AB operated Philips Gen 6 LDMOS device, yielding 44% efficiency at an adjacent channel power level of -45 dBc at 2.14 GHz for an IS-95 signal

Surface-passivated high-resistivity silicon as a true microwave substrate

The performance characteristics of transmission lines, silicon integrated waveguides, tunable LC resonators and passive combiners/splitters and baluns are described in this paper. It is shown that Q-factor for an on-chip LC tank peaks between 20 and 40 GHz in a 65 nm RF-CMOS technology; well below the bands proposed for many mm-wave applications. Simulations also predict that the Q-factor of differential CPW transmission lines on-chip can exceed 20 at 60 GHz in RF-CMOS when a floating shield is applied, outperforming unshielded variants employing more advanced metal stacks. A PA circuit demonstrator for advanced on-chip passive power combiners, splitters and baluns realizes peak-PAE of 18% and Psat better than 20 dBm into a 50 Ω load at 62 GHz. An outlook to the enablement of digitally intensive mm-wave ICs and low-loss passive interconnections (0.15 dB/mm measured loss at 100 GHz) concludes the paper.

Active Harmonic Load–Pull for On-Wafer Out-of-Band Device Linearity Optimization

A three-stage, 60GHz transformer-coupled differential power amplifier is implemented in 130nm SiGe-BiCMOS. Common-base differential pair stages extend BVCEO, while neutralization increases isolation, promoting stability. Self-shielded transformers, a parasitic-compensated 4∶1 output combiner and 2∶4 input splitter are designed for low insertion loss and compact dimensions on-chip. Measured small-signal gain is >20dB with over 10GHz −3dB bandwidth. Reverse isolation is better than 51dB across 50–65GHz. Maximum output power and peak-PAE are 20.5dBm and 20%, respectively, at 61.5GHz. The PA consumes 353mW from a 1.8V supply and 0.25mm2 active area.

Passive Circuit Technologies for mm-Wave Wireless Systems on Silicon

A low-distortion varactor-tuned bandpass filter is demonstrated on a high-Q silicon-on-glass technology. The dc bias network is optimized to achieve high linearity, the center frequency of the filter tunes from 2.4 to 3.5 GHz, and the measured loss of the filter is 2-3 dB at 2 GHz, with a stopband rejection of 25 dB. The measured IIP3 of the filter was +46 dBm

A 60GHz-band 20dBm power amplifier with 20% peak PAE

An optimization procedure based on load-pull measurements to obtain both highly-linear and highly-efficient class-AB operation is presented. This procedure can be applied without any foregoing device characterization; therefore it is an excellent method to compare the linearity performance of different bipolar technologies. The presented approach provides the optimum out-of-band terminations and quiescent current yielding IM3 improvement of more than 15 dBc at 3 dB back-off compared to traditional design techniques. Optimum power-added efficiency is achieved at the same time.