Morteza S. Alavi

A Wideband 2

This paper presents a wideband 2 ×13-bit in-phase/quadrature-phase (I/Q) RF digital-to-analog converter-based all-digital modulator realized in 65-nm CMOS. The isolation between I and Q paths is guaranteed employing 25% duty-cycle differential quadrature clocks. With a 1.3-V supply and an on-chip power combiner, the digital I/Q transmitter provides more than 21-dBm RF output power within a frequency range of 1.36-2.51 GHz. The peak RF output power, overall system, and drain efficiencies of the modulator are 22.8 dBm, 34%, and 42%, respectively. The measured static noise floor is below -160 dBc/Hz. The digital I/Q RF modulator demonstrates an IQ image rejection and local oscillator leakage of -65 and -68 dBc, respectively. It could be linearized using either of the two digital predistortion (DPD) approaches: a memoryless polynomial or a lookup table. Its linearity is examined using single-carrier 4/16/64/256/1024 quadrature amplitude modulation (QAM), as well as multi-carrier 256-QAM orthogonal frequency-division multiplexing baseband signals while their related modulation bandwidth can be as high as 154 MHz. Employing DPD improves the third-order intermodulation product (IM3) by more than 25 dB, while the measured error vector magnitude for a “single-carrier 22-MHz 64-QAM” signal is better than -28 dB.

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We present a new all-digital RF in-phase/quadrature (I/Q) modulator, in which the orthogonal summing of the I and Q phase data signals is performed in separated interleaved time slots. By employing a 25% duty cycle for the I and Q signals, the modulator can directly reconstruct the continuous-time RF output signal using four digital switch arrays with a power combiner. To verify the proposed concept and its related design procedure, a 65-nm CMOS prototype is implemented. This prototype achieves 12.6-dBm peak output power with 20% peak drain efficiency at 2 GHz. The corresponding error vector magnitude (EVM) for a quadrature phase-shift keying constellation is 3.95% without any predistortion, while providing 6-dBm output power in a 64 quadrature amplitude modulation constellation with a related EVM and drain efficiency of 2.36% and 10%, respectively. The proposed circuit can be used as a pre-driver or a final transmit stage. The first-ever truly all-digital I/Q RF digital-to-analog converter prototype is thus experimentally demonstrated.

13-bit All-Digital I/Q RF-DAC

This paper elaborates on the recently introduced concept of an all-digital RF I/Q modulator. Orthogonal summation and design procedure of the power combining network are explained in more detail. A 65 nm CMOS prototype is implemented based on this concept. The prototype achieves 12.6 dBm peak output power and 20% peak drain efficiency at 2 GHz. While providing 6 dBm output power, the error vector magnitude (EVM) is 3.7%.

All-Digital RF

We propose a novel digital I/Q modulator implemented in 65 nm CMOS technology. Using in-phase (I) and quadrature-phase (Q) clock signals with a 25% duty cycle, the modulator can directly construct the RF output signal using four transistor switch banks with a power combiner. The circuit achieves 12.6 dBm peak output power and 20% peak drain efficiency at 2 GHz. While providing 6 dBm output power, the error vector magnitude (EVM) is 3.7% and could be used as pre-driver or final transmit stage. The first ever all-digital I/Q RF-DAC prototype is thus experimentally demonstrated.

I/Q

This paper presents a 2×13-bit I/Q RF-DAC-based all-digital modulator realized in 65 nm CMOS. The proposed quadrature up-converter uses a 25% duty-cycle clock to isolate the in-phase (I) and quadrature-phase (Q) modulating signals before combining. Using a 1.2 V supply and an on-chip power combiner, the modulator provides more than 21 dBm RF output power within a frequency range of 1.36 to 2.51 GHz. The peak RF output power, overall system and drain energy efficiencies of the modulator are 22.3 dBm, 31.5%, and 39.7%, respectively. Applying digital predistortion (DPD), 64 & 256 constellation points are measured with EVM better than -30 dB. The measured noise floor is below -160 dBc/Hz, with an IQ image rejection and LO leakage of -65 and -63 dBc, respectively. Its linearity has been evaluated with WCDMA modulation. Using DPD, the linearity improves by more than 15 dB.

Modulator

We propose a digital I/Q transmitter architecture that avoids area, complexity, noise, distortion and linearity issues of the existing solutions by allocating separate time slots to the I and Q operations during which the respective digitally-controlled RF-switched resistors, realized as arrays of MOS switches, are active. This way, the operational orthogonality of the I and Q paths is maintained and the I/Q switch arrays can be simply connected together. An example silicon realization in 65 nm CMOS uses 25% duty cycle I/Q clocks.

Orthogonal summing and power combining network in a 65-nm all-digital RF I/Q modulator

In this work efficient LDMOS device operation for envelope tracking amplifier systems is discussed. Utilizing the voltage dependence of Cds in combination with a well chosen 2nd harmonic output termination, a “hybrid” combination of class-J* and class-B device operation is defined, which yields improved efficiency at low supply voltages in power back-off, while avoiding device breakdown when operating at high supply voltages. Using these techniques with a Gen7 NXP 2W LDMOS device in a load-pull test bench, more than 63% drain efficiency over a 10 dB power back-off range is achieved at 2.14 GHz. The proposed method is supported by simulations and measurements and is directly applicable to envelope tracking power amplifiers.

A 2-GHz digital I/Q modulator in 65-nm CMOS

In this paper, we present a fully integrated RFDAC-based outphasing power amplifier (ROPA) in 40-nm CMOS that achieves 22.2 dBm peak output power with 49.2% drain efficiency at 5.9 GHz. It employs differential quasi-load-insensitive Class-E branch PAs that can dynamically be segmented using a 3-bit digital amplitude control word to improve efficiency at power back-off. At 8 dB back-off, this segmentation technique improves the ROPA drain and system efficiency by 5% and 7%, respectively, when compared to a non-segmented approach.

A 2×13-bit all-digital I/Q RF-DAC in 65-nm CMOS

To fully benefit from the progress of CMOS technologies, it is desirable to completely digitize the TX, replacing its final stage with a digitally controlled PA (DPA). The DPA consists of arrays of small sub-PAs that are digitally controlled to modulate the output amplitude, thus operating as an RF-DAC [1–6]. DPAs are normally designed in a switched mode (Classes E/D/D−1, etc.) to achieve high efficiency while using high sampling rate to attenuate and push the spectral images to higher frequencies. However, they suffer from high nonlinearity in their AM-code-word (ACW) to AM and ACW-to-PM conversion. To correct for such nonlinearities, digital pre-distortion (DPD) of the input signal is often used [1–3], typically implemented by look-up tables (LUT). Unfortunately, DPD approaches suffer from large signal-BW expansion due to their inherently nonlinear characteristics. This, combined with the already present BW regrowth in a polar TX in the AM and PM paths, yields significant hardware-speed/power constraints when the signal BW becomes large. For a Cartesian TX, the use of LUT-DPD is even more complicated since a full 2D LUT is typically required [2]. To relax the overall system complexity, it is highly desirable to have a PA with a maximum inherent linearity without compromising its power or efficiency. In this work, an ACW-AM correction based on nonlinear sizing along with controlling the peak voltage of RF clocks (overdrive voltage tuning) and a ACW-PM correction based on multiphase RF clocking are introduced to linearize the characteristic curves of a Class-E polar DPA with intent to avoid any kind of pre-distortion.

Digital I/Q RF transmitter using time-division duplexing

This paper presents a wideband linear direct-digital RF modulator (DDRM) in 40-nm CMOS technology. An innovative