Leon Stok

Pushing ASIC performance in a power envelope

Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best power efficiency for high-performance applications. The flexibility of ASICs allow for the use of multiple voltages and multiple thresholds to match the performance of critical regions to their timing constraints, and minimize the power everywhere else. We explore the trade-off between multiple supply voltages and multiple threshold voltages in the optimization of dynamic and static power. The use of multiple supply voltages presents some unique physical and electrical challenges. Level shifters need to be introduced between the various voltage regions. Several level shifter implementations will be shown. The physical layout needs to be designed to ensure the efficient delivery of the correct voltage to various voltage regions. More flexibility can be gained by using appropriate level shifters. We discuss optimization techniques such as clock skew scheduling which can be effectively used to push performance in a power neutral way.

BooleDozer: logic synthesis for ASICs

Logic synthesis is the process of automatically generating optimized logic-level representation from a high-level description. With the rapid advances in integrated circuit technology and the resultant growth in design complexity, designers increasingly rely on logic synthesis to shorten the design time while achieving performance objectives. This paper describes the IBM logic synthesis system BooleDozer™, including its organization, main algorithms, and how it fits into the design process. The BooleDozer logic synthesis system has been widely used within IBM to successfully synthesize processor and ASIC designs.

Wavefront technology mapping

The wavefront technology mapping algorithm leads to a very simple and efficient implementation that elegantly decouples pattern matching and covering but circumvents that patterns have to be stored for the entire network simultaneously. This coupled with dynamic decomposition enables trade-off of many more alternatives than in conventional mapping algorithms. The wavefront algorithm maps optimally for minimal delay on directed acyclic graphs (DAGs) when a gain based delay model is used. It is optimal with respect to the arrival times on each path in the network. A special timing mode for multi-source nets allows minimization of other (non-delay) metrics as a secondary objective while maintaining delay optimality.

Transformational placement and synthesis

Novel methodology and algorithms to seamlessly integrate logic synthesis and physical placement through a transformational approach are presented. Contrary to most placement algorithms that minimize a global cost function based on an abstract representation of the design, we decomposed the placement function into a set of transforms and coupled them directly with incremental timing, noise, and/or power analyzers. This coupling results in a direct and more accurate feedback on optimizations for placement actions. These placement transforms are then integrated with traditional logic synthesis transforms leading to a converging set of optimizations based on the concurrent manipulation of boolean, electrical, as well as physical data. Experimental results indicate that the proposed approach creates an efficient converging design flow that eliminates placement and synthesis iteration. It results in timing improvements, and maintains other global placement measures such as wire congestion and wire length. The flexibility of the transformational approach allows us to easily add, extend and support more sophisticated algorithms that involve critical as well as non-critical regions and target a variety of metrics including noise, yield and manufacturability:.

Retiming revisited and reversed

Retiming is a very promising transformation of circuits which preserves functionality and improves performance. Its benefits are especially promising in automatic synthesis of circuits from higher-level descriptions. However, retiming has not been widely included in current design tools and methodologies. One of the main obstacles is the problem of finding an equivalent initial state for the retimed circuit. In this paper, we introduce a simple modification of the retiming algorithm of Leiserson and Saxe. The modified algorithm helps minimize the effort required to find equivalent initial states and reduces the chance that the network needs to be modified in order to find an equivalent initial state. This algorithm is the kernel of a new efficient retiming method, which searches for optimal retimings while preserving the initial state condition. The paper also presents an improved method to perform the initial state calculation.

Keeping hot chips cool

With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper outline practical techniques that are used to reduce both leakage as well as active power in a standard-cell library based high-performance design flow. We discuss the design and cost issues for using different power saving techniques such as: power gating to reduce leakage, multiple and hybrid threshold libraries for leakage reduction and multiple supply voltage based design. In addition techniques to reduce clock tree power are presented as power consumed in clocks accounts for a significant portion of total chip power. Practical aspects of implementing these techniques is also discussed.

Data path synthesis

Abstract This paper reviews all the phases in data path synthesis: register allocation, storage grouping, module allocation and interconnect allocation. In addition, a new phase for the storage value insertion is introduced. For each of these phases a formal problem description is given. Restrictions on the data path allocation phases are presented, which delimit the problems to cases which can be solved by polynomial algorithms. For the general cases, heuristics are provided which have appeared to be effective in the literature. Special data path architectures may require special algorithms to make use of their features. Throughout the paper archetectural constraints are described and effective algorithms for them derived. To construct an effective data path allocation system, a scheme has to be defined. The scheme determines which subproblems are solved in what order and which constraints are taken into account in each phase. The data flow graph and schedule and their match with the data path architecture have a major impact on the development of a scheme. This paper will point out the trade-offs that have to be made when developing such a scheme. This paper provides a reference to most of the data path allocation algorithms published in the scope of high-level synthesis. Most of the techniques are explained in considerable detail and various examples are given. The paper comments on the applicability of most of the algorithms for particular data path allocation problems.

Foreground memory management in data path synthesis

The management of foreground memory is a main issue in data path synthesis. the storage of values in registers and register files not only determines the number of each of them but also has a major impact on the interconnect structure. Both the amount of multiplexing and interconnect are crucial factors to both the delay and area of a circuit. In this paper it is shown that when values are grouped into register files before being assigned to actual registers, significant savings (20 per cent) can be obtained in the number of local interconnections and the amount of global interconnect at the expense of only slightly more register area. These results can be enhanced by splitting the read and write phases of registers and even more by introducing serial (re)write operations for the same value. the value grouping is based on edge-colouring algorithms that provide a sharp upper bound on the number of register groups needed. After value grouping, the registers are allocated for each register file separately. Algorithms for register allocation published up till now have only considered loop-free data flow graphs. When these algorithms are applied to data flow graphs with loops, unnecessary register transfer operations can be introduced. In this paper a new algorithm is presented that performs a minimal register allocation eliminating all superfluous register transfer operations. Experiments on a benchmark set have shown that in all cases all register transfers could be eliminated at no increase in register cost. This paper provides a deeper insight to the computational complexity of some problems in the area of data path synthesis. It shows that the various subtasks can be solved exactly using polynomial time algorithms.

Interconnect optimisation during data path allocation

In previous research interconnection was optimised when the module allocation for the operations and the register allocation for the variables already had been done. However, both the amount of multiplexing and interconnect are crucial factors to both the delay and the area of a circuit. In this paper it is shown that when variables are grouped into register files and operations are assigned to modules to minimise the interconnections, significant savings (20%) can be obtained in the number of local interconnections and the amount of global interconnect on the expense of only slightly more register area. This can be enhanced by splitting read and write phases of registers and even more by introducing serial (re-) write operations for the same value. The variable grouping is based on edge colouring algorithms that provide a sharp upper bound on the number of colours needed.<<ETX>>

A data flow graph exchange standard

Presents a data flow graph exchange standard, agreed upon and used by the partners in the ESPRIT research project, ASCIS. These data flow graphs are generated from known user interface languages such as Silage, VHDL, and C, and are used to drive architectural synthesis packages and formal verification. The graph semantics are defined to offer a unique degree of freedom for time and area optimizations in synthesis, by giving a maximal parallel representation and combining control and data flow in a consistent way. The graph textual exchange format was developed to allow site and application dependent extensions, without disturbing tools who do not know about these.<<ETX>>