Leonard Masing

Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms

One challenge in developing complex software for embedded systems is the missing option of rapid prototyping in early stages of the development cycle. In this paper we present the use of the High Level Simulation Framework “Open Virtual Platforms” (OVP) for Software-in-the-Loop simulation of embedded control applications. Therefore, we investigate and evaluate different methods allowing the data exchange between the simulated platform and the host machine running the simulation environment. The insights we gain are used to design peripherals which appear to the simulated processor system like devices available on the targeted hardware platform and allow the access to files stored on the host machine on one hand, and the communication with hardware devices connected to the host on the other hand. In both cases the cross-compiled application code for the targeted embedded platform including the operating system (OS) and the hardware abstraction layer (HAL) can be executed by the virtual platform (VP) without any modifications. Additionally, we introduce a method for controlling the synchronization of OVP with the host, which can be used to either run simulations in fast motion mode, or to collaborate with hardware devices or other applications. The approach is verified with two use cases: (1) a motor control application processing data by accessing files and (2) an image processing application interacting with real hardware devices directly coupled with the virtual platform.

Designing applications for heterogeneous many-core architectures with the FlexTiles Platform

The FlexTiles Platform has been developed within a Seventh Framework Programme project which is co-funded by the European Union with ten participants of five countries. It aims to create a self-adaptive heterogeneous many-core architecture which is able to dynamically manage load balancing, power consumption and faulty modules. Its focus is to make the architecture efficient and to keep programming effort low. Therefore, the concept contains a dedicated automated tool-flow for creating both the hardware and the software, a simulation platform that can execute the same binaries as the FPGA prototype and a virtualization layer to manage the final heterogeneous many-core architecture for run-time adaptability. With this approach software development productivity can be increased and thus, the time-to-market and development costs can be decreased. In this paper we present the FlexTiles Development Platform with a many-core architecture demonstration. The steps to implement, validate and integrate two use-cases are discussed.

Fault-tolerant communication in invasive networks on chip

Dependability and fault tolerance will play an ever increasing role when using future technology nodes. The paper presents a fault-tolerance strategy for invasive networks on chip (i-NoC). The strategy focuses on permanent faults, resulting from either process fluctuations or aging effects and briefly outlines counter measurements against transient faults. We propose a scalable scheme for detection and localization of defects in NoCs. The localization scheme is used as a basis for disabling faulty routers. We propose a transparent bypass scheme to circumvent faulty routers and regions. It uses an architecture extension in the form of an additional lightweight network layer. The fault tolerance layer can be configured at run time according to the current fault map of the architecture. The presented evaluations analyze the fault coverage of the proposed detection and localization strategy. We also investigate the implementation cost and performance impact of the fault tolerance network layer.

Virtual prototyping of heterogeneous dynamic platforms using Open Virtual Platforms

Heterogeneous dynamic computing platforms are one of the big trends in todays electronic world. These platforms typically feature different General-Purpose-Processors (GPP) combined with accelerators on a reconfigurable layer. However, this necessitates specialized programming models and an Operating System (OS) for dealing with the dynamicity. To allow the early development of the system software, the tool-chain and to help in the design space exploration, high-level simulations offer a possible solution. In this paper we evaluate the application of Open Virtual Platforms (OVP) for the modelling of a heterogeneous dynamic platform. The OVP high-level simulations are extended by introducing peripherals to model the abilities of such a platform. Specifically, a generic I/O device, a communication device for a distributed platform and an accelerator interface with a reconfigurable accelerator model is implemented and integrated into a simulated platform. Different approaches are presented and the insights and results gained during the development process are discussed regarding speed and applicability to the use case.

OpenMPspy: Leveraging quality assurance for parallel software

OpenMP is widely used in practice to create parallel software, however, software quality assurance tool support is still immature. OpenMPspy introduces a new approach, with a short-term and a long-term perspective, to aid software engineers write better parallel programs in OpenMP. On the one hand, OpenMPspy acts like an online-debugger that statically detects problems with incorrect construct usage and which reports problems while programmers are typing code in Eclipse. We detect simple slips as well as more complex anti-patterns that can lead to correctness problems and performance problems. In addition, OpenMPspy can aggregate statistics about OpenMP language usage and bug patterns from many projects. Insights generated from such data help OpenMP language designers improve the usability of constructs and reduce error potential, thus enhancing parallel software quality in the long run. Using OpenMPspy, this paper presents one of the first detailed empirical studies of over 40 programs with more than 4 million lines of code, which shows how OpenMP constructs are actually used in practice. Our results reveal that constructs believed to be frequently used are actually rarely used. Our insights give OpenMP language and compiler designers a clearer picture on where to focus the efforts for future improvements.

OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures

Heterogeneous architectures featuring multiple hardware accelerators have been proposed as a promising solution for meeting the ever-increasing performance and power requirements of embedded systems. However, the existence of numerous design parameters may result in different architectural schemes and thus in extra design effort. To address this issue, OpenCL-based frameworks have been recently utilized for FPGA programming, to enable the portability of a source code to multiple architectures. However, such OpenCL frameworks focus on RTL design, thus not enabling rapid prototyping and abstracted modeling of complex systems. Virtual Prototyping aims to overcome this problem by enabling the system modeling in higher abstraction levels. This article combines the benefits of OpenCL and Virtual Prototyping, by proposing an OpenCL-based prototyping framework for data-parallel many-accelerator systems, which (a) creates a SystemC Virtual Platform from OpenCL, (b) provides a co-simulation environment for the host and the Virtual Platform, (c) offers memory and interconnection models for parallel data processing, and (d) enables the system evaluation with alternative real number representations (e.g., fixed-point or 16-bit floating-point).