Leopoldo D. Yau

Process-induced distortion in silicon wafers

As the packing density of integrated circuits increases so does the need for increasingly accurate registration between lithographic steps. In-plane wafer distortion between such steps can limit this accuracy depending on the lithographic technique used and on the nature of the distortion. The in-plane distortion of 3-in silicon wafers at different stages of a simulated n-MOS process sequence was measured directly using the Bell Laboratories Electron-Beam Exposure System (EBES). The results indicate that the in-plane wafer distortion was linear (to within the overall EBES reading noise of ± ⅛ µm per axis). The radius of curvature of each wafer was measured independently. The wafer distortion is correlated to the change in curvature induced by the films grown or deposited on the wafer. After these films were removed, the wafers reverted to their original dimensions. Since the wafer diameter is at least two orders of magnitude smaller than the radius of curvature, a linear correction is still a good approximation. Therefore, even though the process-induced changes in vector lengths were as high as 1 µm over 50 mm, the three-point alignment strategy employed by EBES is sufficient to achieve a maximum registration error on the wafers of ¼ µm or less.

Hot-carrier degradation of submicrometer p-MOSFETs with thermal/LPCVD composite oxide

It is shown that while gate oxides containing thermal/LPCVD composite oxide have lower defect densities than gates using only thermal oxides, they are more susceptible to hot-carrier degradation. The hot-carrier-induced degradation of composite oxides is worse in p-channel MOSFETs than in n-channel MOSFETs. This sensitivity of p-channel MOSFETs is caused by higher electron trapping levels in LPCVD oxides. For 150-AA gate technology, the hot-carrier-degradation resistance of thermal/LPCVD composite gate oxides with a 70-AA or thicker thermal oxide layer approaches that of high-quality pure thermal oxide. >